Thư viện tài liệu, ebook tổng hợp lớn nhất Việt Nam

Cray Supercomputers Vector operation may start as soon as first element of operand vector available and functional unit is free Result from one functional unit is fed immediately into another If vector registers used, intermediate results do not have to be stored in memory

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Superscalar features Six wide, ten stage deep hardware pipeline Dynamic prefetch branch prediction register scoreboard to optimise for compile time nondeterminism EPIC features Hardware support for predicated execution Control and data speculation Software pipelining

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Direct descendent of IBM 801, RT PC and RS/6000 All are RISC RS/6000 first superscalar PowerPC 601 superscalar design similar to RS/6000 Later versions extend superscalar concept

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Quantitative compare program sizes and execution speeds Qualitative examine issues of high level language support and use of VLSI real estate Problems No pair of RISC and CISC that are directly comparable No definitive set of test programs Difficult to separate hardware effects from complier effects Most comparisons done on “toy” rather tha...

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Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity

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Pentium (80x86), VAX are little-endian IBM 370, Moterola 680x0 (Mac), and most RISC are big-endian Internet is big-endian Makes writing Internet programs on PC more awkward! WinSock provides htoi and itoh (Host to Internet & Internet to Host) functions to convert

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Standard for floating point storage 32 and 64 bit standards 8 and 11 bit exponent respectively Extended formats (both mantissa and exponent) for intermediate results

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Stallings chapter 8 Stallings, W. Operating Systems, Internals and Design Principles, Prentice Hall 1998 Loads of Web sites on Operating Systems

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Wide variety of peripherals Delivering different amounts of data At different speeds In different formats All slower than CPU and RAM Need I/O modules

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Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package – all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps Asynchronous block protocol 480ns access time Then 1.6 Gbps

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