The method of controlling counter restructure in parallel processing system

Bùi Minh Quý và Đtg Tạp chí KHOA H ỌC & CÔNG NGH Ệ 93(05): 11 - 15 THE METHOD OF CONTROLLING COUNTER RESTRUCTURE IN PARALLEL PROCESSING SYSTEM Chu Duc Toan * Electric Power University ABSTRACT In parallel processing systems, the efficient use of system resources is an important requirement. Improving performance and increasing speed are related to many issues, both hardware and software [1, 2]. The analysis of processing system operation shows which affects the performance and speed of processing system: During referencing to memory, the processor uses only a command cycle in order to require to read or write data into memory, then wait for the completion of memory cycle before next memory access. Therefore, CPU speed is not taken full advantage; memory access conflicts occur when two or more components simultaneously access to a memory location. This paper proposes the method of controlling counter restructure to meet the requirements of information processing speed. The model used is a restructure controller with FPGA technology. The solution of speed increase is done by maintaining the maximized chain of memory access requests. Keywords : restructure controller with FPGA technology; speed; parallel processing system; performance; the mechanism of parallel memory controller. INTRODUCTION associated with a data latch. The data from Current processing systems have a big each module is delivered through latch and difference between the operation speed of multiplexer to a single data channel. processor and that of memory operations. Figure 2 shows a time graph for many- word This rate is generally from 5 to 15 times [4, reading accesses using S- access 5]. To take full advantage of processor time, configuration. Suppose that the memory the memory is organized in parallel as an access time T and latch delay time τ , time to a + τ interleaving model with S-access memory access a single data word is Ta . However, architecture. This is a solution for memory the total time to access the next string k word, conflicts in accordance with parallel memory starting at module i, is T+ k . τ if i+ k ≤ M , a ++− τ models in parallel processing systems. and opposite case is 2Ta ( i k M ) . In S-access model using lower interleaving both cases, (M is the ratio of CPU speed and address order is described in Figure 1. S- memory speed). The condition to access τ ≤ access method allows all modules to be vectors efficiently is M T a , if not data accessed simultaneously. Each module is overflow will occur [3]. Data latch Module 0 Module 1 Multiplexer Data channel Module 2 m-1 m bits lower address Write - read n-m bits control * Higher address Figure 1. S - Access Memory configuration * Tel: 0982917093, Email: toancd@epu.edu.vn 17 Số hóa bởi Trung tâm Học liệu – Đại học Thái Nguyên Chu Đức Toàn Tạp chí KHOA H ỌC & CÔNG NGH Ệ 93(05): 17 - 21 Access 1 Access 2 Module M-1 Access 1 Access 2 Module 0 W0 WM-1 W0 WM-1 Output Tr ễ truy nh ập kh ởi đầ u Word Access 1 Word R Access 2 Figure 2. Time scheme for S - access configuration Figure 3. Parallel memory control structure in M coefficient combining method An A5 of memory A5 A4 of memory A4 A3 of memory A3 A2 of memory A2 A1 of memory A1 A0 of memory A0 A3 A MUTIPLEXER Rearrangement of control block 2 A1 architecture in FPGA technology A0 Figure 4. Rearrangement of control block architecture in FPGA technology for memory module M = 16 = 2 4 18 Số hóa bởi Trung tâm Học liệu – Đại học Thái Nguyên Bùi Minh Quý và Đtg Tạp chí KHOA H ỌC & CÔNG NGH Ệ 93(05): 11 - 15 THE STRUCTURE OF PARALLEL technology for memory module M = 16 is MEMORY CONTROL SYSTEM illustrated in Figure 3 and Figure 4. Considering a typical and enough structure Processing mode: for a system shown in Figure 3. Assuming the In this mode, specific control partition for ratio of CPU speed and memory speed is M, χ address channel and system control channel is is the probability that a next request accesses described in detail in Table 1 the next memory modules, θ is the probability Where: Addr Multiplexer is a pointer to that a next request accesses a determined memory module corresponding requirements memory module, but not the next memory and SCAN Multiplexer allows right access as module. scanning cycle to ensure memory recovery To improve the performance of data flow, time. considering the characteristics of the system * Information collection: with the assistance of FPGA technology, we can create software architecture for When switching to information collecting, information collecting and information specific control partition for address channel processing. Parallel memory control structure and system control channel in this mode is followed the combination method with M described in detail in Table 2 factor and restructure control block in FPGA Table 1 . Address processing mode control Addr Multiplexer Memory module Circuit connection E0 m a0 a1 a (2 -1) A0 A1 Address channel and 1 A0 A1 A( m ) A( m) A( m ) system control channel 2 -1 2 (2 +1 Table 2 . Address information collecting mode control Addr Multiplexer Memory module Circuit connection E0 m m m m a0 a1 a(2 -1) A0 A1 A( 2 -1) A( 2 ) A( (2 +1 ) Address channel and 0 x x x A A A( m ) A( m) A( m ) system control channel 0 1 2 -1 2 (2 +1 Memory module # 0 t W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Memory module # 1 t W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Memory module # 2 t W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Memory module # 15 t W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Figure 5. Time graph of information recording into memory 19 Số hóa bởi Trung tâm Học liệu – Đại học Thái Nguyên Chu Đức Toàn Tạp chí KHOA H ỌC & CÔNG NGH Ệ 93(05): 17 - 21 Memory module # 0 the left W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Memory module # 1 the left W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Memory module # 2 W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Memory module # 15 module not accessible W00 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 Figure 6. The time graph for the process of reading information from memory After collection is complete, to read the data in one direction, the system optimization is just follow 2- step algorithm: nearly absolute by the aid of FPGA Step 1. Copy data from 16 memory modules technology with system architecture in corresponding position on each other. As a rearrangement technique. Architecture result, we have 16 data regions containing rearrangement control system by FPGA same content. always requires data read/ write line to achieve maximum value k = max = constant. Step 2. Composite address channel as table by FPGA technology. The result is that memory space is organized into 16 parallel standard REFERENCES memory modules and reading process [1]. Barry W. (1996), “ Computer architecture design and performance ”, University of North conducts as normal. Carolina, Prentice Hall, New York. Suppose to retrieve data as the order of [2]. Chou Y., Fahs B., AND Abraham S. (2004), memory access request sequence with address “Microarchitecutre optimizations for exploiting 00, 02, 04, 06, 08, 10, 12, 14, 16 ... then the memory-level parallelism”. ACM pp. 29-70. system will ignore the modules # 1, # 3 , # 5, [3]. Hamacher, C., Vranesic, Z., Zaky, S. # 7, # 9, # 11, # 13, # 15, although there are (2002), Computer Organization , McGraw-Hill, Inc., New York. full of original data. [4]. Mehdi R. Zargham, (2001), Computer In this case the length of request string k is only Architecture Single and Parallel Systems , Southem 8, equal to half of maximum value of k (= 16). Illinois University, Prentice-Hall. Inc., London. [5]. Rao G. S. (1998), “Performance Analysis of CONCLUSION Cache Memories.” Journ. of Assoc. of Comp. This paper proposes degradation processing Mach., vol. 25. no.3, pp. 378-397. system. When the task of processing is only 20 Số hóa bởi Trung tâm Học liệu – Đại học Thái Nguyên Chu Đức Toàn Tạp chí KHOA H ỌC & CÔNG NGH Ệ 93(05): 17 - 21 MỘT PH ƯƠ NG PHÁP ĐIỀU KHI ỂN TÁI KI ẾN TRÚC B Ộ ĐẾ M TRONG H Ệ X Ử LÝ SONG SONG Chu Đức Toàn * Đại h ọc Điện l ực TÓM T ẮT Trong các h ệ x ử lý song song, vi ệc s ử d ụng hi ệu qu ả các tài nguyên h ệ th ống là yêu cầu h ết s ức quan tr ọng. Vi ệc nâng cao hi ệu n ăng, nâng cao t ốc độ g ồm nhi ều v ấn đề , liên quan c ả đế n ph ần cứng và ph ần m ềm [1, 2]. Phân tích ho ạt độ ng c ủa h ệ x ử lý cho th ấy nguyên nhân làm ảnh h ưởng đến hi ệu n ăng, t ốc độ c ủa h ệ x ử lý là: quá trình tham chi ếu đế n b ộ nh ớ, b ộ x ử lý ch ỉ s ử d ụng m ột chu k ỳ l ệnh để yêu c ầu đọ c ho ặc ghi d ữ li ệu vào b ộ nh ớ, sau đó ph ải ch ờ chu k ỳ b ộ nh ớ k ết thúc tr ước khi có th ể truy c ập ti ếp b ộ nh ớ. Do đó, không t ận d ụng tri ệt để t ốc độ c ủa CPU; xung độ t truy c ập b ộ nh ớ x ảy ra khi có hai hay nhi ều thành ph ần đồ ng th ời truy c ập t ới m ột v ị trí nh ớ. Bài báo đề xu ất ph ươ ng pháp điều khi ển tái ki ến trúc b ộ đế m nh ằm đáp ứng yêu c ầu t ốc độ x ử lý thông tin. Mô hình được dùng là b ộ điều khi ển tái ki ến trúc b ằng công ngh ệ FPGA, gi ải pháp t ăng t ốc độ được th ực hi ện b ằng cách duy trì chu ỗi yêu c ầu truy c ập b ộ nh ớ luôn đạ t c ực đạ i. Từ khóa : Điều khi ển tái ki ến trúc b ằng công ngh ệ FPGA; t ốc độ ; h ệ x ử lý song song; hi ệu n ăng; cơ c ấu điều khi ển b ộ nh ớ song song. Ngày nh ận bài: 24/2/2012, ngày ph ản bi ện: 14/3/2012, ngày duy ệt đă ng: * Tel: 0982917093, Email: toancd@epu.edu.vn 21 Số hóa bởi Trung tâm Học liệu – Đại học Thái Nguyên