William stallings computer organization and architecture 6th edition - Chapter 7: Input/ Output

William Stallings Computer Organization and Architecture6th EditionChapter 7Input/OutputInput/Output ProblemsWide variety of peripheralsDelivering different amounts of dataAt different speedsIn different formatsAll slower than CPU and RAMNeed I/O modulesInput/Output ModuleInterface to CPU and MemoryInterface to one or more peripheralsGeneric Model of I/O ModuleExternal DevicesHuman readableScreen, printer, keyboardMachine readableMonitoring and controlCommunicationModemNetwork Interface Card (NIC)External Device Block DiagramTypical I/O Data RatesI/O Module FunctionControl & TimingCPU CommunicationDevice CommunicationData BufferingError DetectionI/O StepsCPU checks I/O module device statusI/O module returns statusIf ready, CPU requests data transferI/O module gets data from deviceI/O module transfers data to CPUVariations for output, DMA, etc.I/O Module DiagramI/O Module DecisionsHide or reveal device properties to CPUSupport multiple or single deviceControl device functions or leave for CPUAlso O/S decisionse.g. Unix treats everything it can as a fileInput Output TechniquesProgrammedInterrupt drivenDirect Memory Access (DMA)Programmed I/OCPU has direct control over I/OSensing statusRead/write commandsTransferring dataCPU waits for I/O module to complete operationWastes CPU timeProgrammed I/O - detailCPU requests I/O operationI/O module performs operationI/O module sets status bitsCPU checks status bits periodicallyI/O module does not inform CPU directlyI/O module does not interrupt CPUCPU may wait or come back laterI/O CommandsCPU issues addressIdentifies module (& device if >1 per module)CPU issues commandControl - telling module what to doe.g. spin up diskTest - check statuse.g. power? Error?Read/WriteModule transfers data via buffer from/to deviceAddressing I/O DevicesUnder programmed I/O data transfer is very like memory access (CPU viewpoint)Each device given unique identifierCPU commands contain identifier (address)I/O MappingMemory mapped I/ODevices and memory share an address spaceI/O looks just like memory read/writeNo special commands for I/OLarge selection of memory access commands availableIsolated I/OSeparate address spacesNeed I/O or memory select linesSpecial commands for I/OLimited setInterrupt Driven I/OOvercomes CPU waitingNo repeated CPU checking of deviceI/O module interrupts when readyInterrupt Driven I/OBasic OperationCPU issues read commandI/O module gets data from peripheral whilst CPU does other workI/O module interrupts CPUCPU requests dataI/O module transfers dataCPU ViewpointIssue read commandDo other workCheck for interrupt at end of each instruction cycleIf interrupted:-Save context (registers)Process interruptFetch data & storeSee Operating Systems notesDesign IssuesHow do you identify the module issuing the interrupt?How do you deal with multiple interrupts?i.e. an interrupt handler being interruptedIdentifying Interrupting Module (1)Different line for each modulePCLimits number of devicesSoftware pollCPU asks each module in turnSlowIdentifying Interrupting Module (2)Daisy Chain or Hardware pollInterrupt Acknowledge sent down a chainModule responsible places vector on busCPU uses vector to identify handler routineBus MasterModule must claim the bus before it can raise interrupte.g. PCI & SCSIMultiple InterruptsEach interrupt line has a priorityHigher priority lines can interrupt lower priority linesIf bus mastering only current master can interruptExample - PC Bus80x86 has one interrupt line8086 based systems use one 8259A interrupt controller8259A has 8 interrupt linesSequence of Events8259A accepts interrupts8259A determines priority8259A signals 8086 (raises INTR line)CPU Acknowledges8259A puts correct vector on data busCPU processes interruptISA Bus Interrupt SystemISA bus chains two 8259As togetherLink is via interrupt 2Gives 15 lines16 lines less one for linkIRQ 9 is used to re-route anything trying to use IRQ 2Backwards compatibilityIncorporated in chip set82C59A InterruptControllerIntel 82C55A Programmable Peripheral InterfaceUsing 82C55A To Control Keyboard/DisplayDirect Memory AccessInterrupt driven and programmed I/O require active CPU interventionTransfer rate is limitedCPU is tied upDMA is the answerDMA FunctionAdditional Module (hardware) on busDMA controller takes over from CPU for I/ODMA Module DiagramDMA OperationCPU tells DMA controller:-Read/WriteDevice addressStarting address of memory block for dataAmount of data to be transferredCPU carries on with other workDMA controller deals with transferDMA controller sends interrupt when finishedDMA TransferCycle StealingDMA controller takes over bus for a cycleTransfer of one word of dataNot an interruptCPU does not switch contextCPU suspended just before it accesses busi.e. before an operand or data fetch or a data writeSlows down CPU but not as much as CPU doing transferAsideWhat effect does caching memory have on DMA?Hint: how much are the system buses available?DMA Configurations (1)Single Bus, Detached DMA controllerEach transfer uses bus twiceI/O to DMA then DMA to memoryCPU is suspended twiceDMA Configurations (2)Single Bus, Integrated DMA controllerController may support >1 deviceEach transfer uses bus onceDMA to memoryCPU is suspended onceDMA Configurations (3)Separate I/O BusBus supports all DMA enabled devicesEach transfer uses bus onceDMA to memoryCPU is suspended onceI/O ChannelsI/O devices getting more sophisticatede.g. 3D graphics cardsCPU instructs I/O controller to do transferI/O controller does entire transferImproves speedTakes load off CPUDedicated processor is fasterI/O Channel ArchitectureInterfacingConnecting devices togetherBit of wire?Dedicated processor/memory/buses?E.g. FireWire, InfiniBandIEEE 1394 FireWireHigh performance serial busFastLow costEasy to implementAlso being used in digital cameras, VCRs and TVFireWire ConfigurationDaisy chainUp to 63 devices on single portReally 64 of which one is the interface itselfUp to 1022 buses can be connected with bridgesAutomatic configurationNo bus terminatorsMay be tree structureSimple FireWire ConfigurationFireWire 3 Layer StackPhysicalTransmission medium, electrical and signaling characteristicsLinkTransmission of data in packetsTransactionRequest-response protocolFireWire Protocol StackFireWire - Physical LayerData rates from 25 to 400MbpsTwo forms of arbitrationBased on tree structureRoot acts as arbiterFirst come first servedNatural priority controls simultaneous requestsi.e. who is nearest to rootFair arbitrationUrgent arbitrationFireWire - Link LayerTwo transmission typesAsynchronousVariable amount of data and several bytes of transaction data transferred as a packetTo explicit addressAcknowledgement returnedIsochronousVariable amount of data in sequence of fixed size packets at regular intervalsSimplified addressingNo acknowledgementFireWire SubactionsInfiniBandI/O specification aimed at high end serversMerger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel)Version 1 released early 2001Architecture and spec. for data flow between processor and intelligent I/O devicesIntended to replace PCI in serversIncreased capacity, expandability, flexibilityInfiniBand ArchitectureRemote storage, networking and connection between serversAttach servers, remote storage, network devices to central fabric of switches and linksGreater server densityScalable data centreIndependent nodes added as requiredI/O distance from server up to 17m using copper300m multimode fibre optic10km single mode fibreUp to 30GbpsInfiniBand Switch FabricInfiniBand Operation16 logical channels (virtual lanes) per physical linkOne lane for management, rest for dataData in stream of packetsVirtual lane dedicated temporarily to end to end transferSwitch maps traffic from incoming to outgoing laneInfiniBand Protocol StackForeground ReadingCheck out Universal Serial Bus (USB)Compare with other communication standards e.g. Ethernet