Hệ điều hành - Chapter 4: Memory management

Memory ManagementChapter 44.1 Basic memory management4.2 Swapping4.3 Virtual memory4.4 Page replacement algorithms4.5 Modeling page replacement algorithms4.6 Design issues for paging systems4.7 Implementation issues4.8 Segmentation1Memory Management Ideally programmers want memory that islargefastnon volatileMemory hierarchy small amount of fast, expensive memory – cache some medium-speed, medium price main memorygigabytes of slow, cheap disk storageMemory manager handles the memory hierarchy2Basic Memory ManagementMonoprogramming without Swapping or PagingThree simple ways of organizing memory- an operating system with one user process3Multiprogramming with Fixed PartitionsFixed memory partitionsseparate input queues for each partitionsingle input queue4Modeling MultiprogrammingCPU utilization as a function of number of processes in memoryDegree of multiprogramming5Analysis of Multiprogramming System PerformanceArrival and work requirements of 4 jobsCPU utilization for 1 – 4 jobs with 80% I/O waitSequence of events as jobs arrive and finishnote numbers show amout of CPU time jobs get in each interval6Relocation and ProtectionCannot be sure where program will be loaded in memoryaddress locations of variables, code routines cannot be absolutemust keep a program out of other processes’ partitionsUse base and limit valuesaddress locations added to base value to map to physical addraddress locations larger than limit value is an error7Swapping (1)Memory allocation changes as processes come into memoryleave memoryShaded regions are unused memory8Swapping (2)Allocating space for growing data segmentAllocating space for growing stack & data segment9Memory Management with Bit MapsPart of memory with 5 processes, 3 holestick marks show allocation unitsshaded regions are freeCorresponding bit mapSame information as a list10Memory Management with Linked ListsFour neighbor combinations for the terminating process X11Virtual MemoryPaging (1)The position and function of the MMU12Paging (2)The relation betweenvirtual addressesand physical memory addres-ses given bypage table13Page Tables (1)Internal operation of MMU with 16 4 KB pages14Page Tables (2)32 bit address with 2 page table fieldsTwo-level page tablesSecond-level page tablesTop-level page table15Page Tables (3)Typical page table entry16TLBs – Translation Lookaside BuffersA TLB to speed up paging17Inverted Page TablesComparison of a traditional page table with an inverted page table18Page Replacement AlgorithmsPage fault forces choice which page must be removedmake room for incoming pageModified page must first be savedunmodified just overwrittenBetter not to choose an often used pagewill probably need to be brought back in soon19Optimal Page Replacement AlgorithmReplace page needed at the farthest point in futureOptimal but unrealizableEstimate by logging page use on previous runs of processalthough this is impractical20Not Recently Used Page Replacement AlgorithmEach page has Reference bit, Modified bitbits are set when page is referenced, modifiedPages are classifiednot referenced, not modifiednot referenced, modifiedreferenced, not modifiedreferenced, modifiedNRU removes page at randomfrom lowest numbered non empty class21FIFO Page Replacement AlgorithmMaintain a linked list of all pages in order they came into memoryPage at beginning of list replacedDisadvantagepage in memory the longest may be often used22Second Chance Page Replacement AlgorithmOperation of a second chancepages sorted in FIFO orderPage list if fault occurs at time 20, A has R bit set(numbers above pages are loading times)23The Clock Page Replacement Algorithm24Least Recently Used (LRU)Assume pages used recently will used again soonthrow out page that has been unused for longest timeMust keep a linked list of pagesmost recently used at front, least at rearupdate this list every memory reference !!Alternatively keep counter in each page table entrychoose page with lowest value counterperiodically zero the counter25Simulating LRU in Software (1)LRU using a matrix – pages referenced in order 0,1,2,3,2,1,0,3,2,326Simulating LRU in Software (2)The aging algorithm simulates LRU in softwareNote 6 pages for 5 clock ticks, (a) – (e)27The Working Set Page Replacement Algorithm (1)The working set is the set of pages used by the k most recent memory referencesw(k,t) is the size of the working set at time, t28The Working Set Page Replacement Algorithm (2)The working set algorithm29The WSClock Page Replacement AlgorithmOperation of the WSClock algorithm30Review of Page Replacement Algorithms31Modeling Page Replacement AlgorithmsBelady's AnomalyFIFO with 3 page framesFIFO with 4 page framesP's show which page references show page faults32Stack AlgorithmsState of memory array, M, after each item in reference string is processed 7 4 6 5 33The Distance StringProbability density functions for two hypothetical distance strings34The Distance StringComputation of page fault rate from distance stringthe C vectorthe F vector35Design Issues for Paging SystemsLocal versus Global Allocation Policies (1)Original configurationLocal page replacementGlobal page replacement36Local versus Global Allocation Policies (2)Page fault rate as a function of the number of page frames assigned37Load ControlDespite good designs, system may still thrashWhen PFF algorithm indicates some processes need more memory but no processes need lessSolution :Reduce number of processes competing for memoryswap one or more to disk, divide up pages they heldreconsider degree of multiprogramming38Page Size (1)Small page sizeAdvantagesless internal fragmentation better fit for various data structures, code sectionsless unused program in memoryDisadvantagesprograms need many pages, larger page tables39Page Size (2)Overhead due to page table and internal fragmentationWheres = average process size in bytesp = page size in bytese = page entrypage table spaceinternal fragmentationOptimized when40Separate Instruction and Data SpacesOne address spaceSeparate I and D spaces41Shared PagesTwo processes sharing same program sharing its page table42Cleaning PolicyNeed for a background process, paging daemonperiodically inspects state of memoryWhen too few frames are freeselects pages to evict using a replacement algorithmIt can use same circular list (clock) as regular page replacement algorithmbut with diff ptr43Implementation IssuesOperating System Involvement with PagingFour times when OS involved with pagingProcess creationdetermine program sizecreate page tableProcess executionMMU reset for new processTLB flushedPage fault timedetermine virtual address causing faultswap target page out, needed page inProcess termination timerelease page table, pages44Page Fault Handling (1)Hardware traps to kernelGeneral registers savedOS determines which virtual page neededOS checks validity of address, seeks page frameIf selected frame is dirty, write it to disk45Page Fault Handling (2)OS brings schedules new page in from diskPage tables updatedFaulting instruction backed up to when it began Faulting process scheduledRegisters restoredProgram continues46Instruction BackupAn instruction causing a page fault47Locking Pages in MemoryVirtual memory and I/O occasionally interactProc issues call for read from device into bufferwhile waiting for I/O, another processes starts uphas a page faultbuffer for the first proc may be chosen to be paged outNeed to specify some pages lockedexempted from being target pages48Backing Store(a) Paging to static swap area(b) Backing up pages dynamically49Separation of Policy and MechanismPage fault handling with an external pager50Segmentation (1)One-dimensional address space with growing tablesOne table may bump into another51Segmentation (2)Allows each table to grow or shrink, independently52Segmentation (3)Comparison of paging and segmentation53Implementation of Pure Segmentation(a)-(d) Development of checkerboarding(e) Removal of the checkerboarding by compaction54Segmentation with Paging: MULTICS (1)Descriptor segment points to page tablesSegment descriptor – numbers are field lengths55Segmentation with Paging: MULTICS (2)A 34-bit MULTICS virtual address56Segmentation with Paging: MULTICS (3)Conversion of a 2-part MULTICS address into a main memory address57Segmentation with Paging: MULTICS (4)Simplified version of the MULTICS TLBExistence of 2 page sizes makes actual TLB more complicated58Segmentation with Paging: Pentium (1)A Pentium selector59Segmentation with Paging: Pentium (2)Pentium code segment descriptorData segments differ slightly60Segmentation with Paging: Pentium (3)Conversion of a (selector, offset) pair to a linear address61Segmentation with Paging: Pentium (4)Mapping of a linear address onto a physical address62Segmentation with Paging: Pentium (5)Protection on the PentiumLevel63