Digital Logic Design - Lecture 25: Shift Registers

Lecture 25Shift RegistersOverviewMultiple flip flops can be combined to form a data register Shift registers allow data to be transported one bit at a timeRegisters also allow for parallel transfer Many bits transferred at the same timeShift registers can be used with adders to build arithmetic unitsRemember: most digital hardware can be built from combinational logic (and, or, invert) and flip flopsBasic components of most computersRegister with Parallel LoadRegister: Group of Flip-FlopsEx: D Flip-FlopsHolds a Word (Nibble) of DataLoads in Parallel on ClockTransitionAsynchronous Clear (Reset)The transfer of new information into a register is referred to as loading the registerRegister with Parallel LoadAll the bits of the register are loaded simultaneously with a single clock pulse, the loading is parallelFor each I that is equal to 1, the corresponding flip-flop inputs are S = 1, R = 0. For each I that is equal to 0, the corresponding flip-flop inputs are S = 0, R = 1. Thus, the input value is transferred into the register provided the load input is 1 and the clear input is 1 CP input acts as an enable signal that controls the loading of new information into the register. When CP goes to 1, the input information is loaded intothe register. If CP remains at 0, the content of the register is not changed.The load input goes through a buffer gate (to reduce loading) and through a series ofAND gates to the Rand S inputs of each flip-flop. Although If the load input is 0, both R and S are 0, and no change of state occurs with anyclock pulse.Register with Load Control Load Control = 1New data loadedon next positiveclock edge Load Control = 0 Old data reloadedon next positiveclock edge The feedback connection in each flip-flop is necessary when a D type is used because a D flip-flop does not have a "no change"input condition.Sequential-Logic ImplementationSince registers are readily available as MSI circuits, it becomes convenient at times to employ a register as part of the sequential circuit.The present state of the register and the external inputs determine the next state of the register and the values of external outputsPart of the combinational circuit determines the next state and the other part generates the outputs. The next state value from the combinational circuit is loaded into the register with a clock pulse.If the register has a load input, it must be set to I; otherwise, if the register has no load input, the next state value will be transferred automatically every clock pulse.ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:ExampleDesign the sequential circuit whose state table is listed in Fig. The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information is obtained directly from the table:Shift RegistersCascade chain of Flip-FlopsBits travel on Clock edgesSerial in – Serial out, can also have parallel load / read Serial Transfer Serial TransferParallel Data TransferAll data transfers on rising clock edgeData clocked into register YParallel versus SerialSerial communications is defined as Provides a binary number as a sequence of binary digits, one after another, through one data line.Parallel communications Provides a binary number through multiple data lines at the same time.parallel inputsparallel outputsserial transmissionShift register applicationParallel-to-serial conversion for serial transmissionSerial Transfer of DataTransfer from register X to register Y (negative clock edges for this example)DQDQDQDQINOUT1OUT2OUT3OUT4CLKOUTPattern recognizerCombinational function of input samplesin this case, recognizing the pattern 1001 on the single input signalClk IN OUT1 OUT2 OUT3 OUT4 OUTBefore 1 1 0 0 0 0 0 2 0 1 0 0 0 0 3 0 0 1 0 0 0 4 1 0 0 1 0 0 5 0 1 0 0 1 1Pattern recognizerCombinational function of input samplesin this case, recognizing the pattern 100011 on the single input signal6 flip-Flops are required7 clock pulses Serial Addition (D Flip-Flop)Slower than parallelLow costShare fasthardware onslow dataGood for multiplexed data Serial Addition (D Flip-Flop)Only one full adderReused for each bitStart with low-order bit additionNote that carry (Q) is savedAdd multiple values.New values placed in shift register BSerial Addition (D Flip-Flop)Shift control used to stop additionGenerally not a good idea to gate the clockShift register can be arbitrary lengthFA can be built from combin. logic Design a serial adder using a sequential-logic procedureTwo shift registers are required to store the binary numbers to be added serially. serial outputs from the registers are designated by variables x and yTwo inputs, x and y, that provide a pair of significant bits, an output S that generates the sum bit, and Hip-flop Q for storing the carry. The present state of Q provides the present value of the carry. The clock pulse that shift the registers enables flip-flop Q to load the next carry. This carry is then used with the next pair of bits in x and y. The state table that specifies the sequential circuit is given in Table Design a serial adder using a sequential-logic procedure Design a serial adder using a sequential-logic procedure Design a serial adder using a sequential-logic procedure Design a serial adder using a sequential-logic procedureUniversal Shift RegisterClearClockShiftRightLeftLoadReadControlUniversal Shift RegisterClearClockShiftRightLeftLoadReadControlSummaryShift registers can be combined together to allow for data transferSerial transfer used in modems and computer peripherals (e.g. mouse)D flip flops allow for a simple designData clocked in during clock transition (rising or falling edge)Serial addition takes less chip area but is slowUniversal shift register allows for many operationsThe register is programmable.It allows for different operations at different times