Phần cứng - Chapter 2: Instruction set

Computer ArchitectureChapter 2Instruction SetsProf. Jerry BreecherCSCI 240Fall 2003Chap. 2 - Instruction Sets*Introduction2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The MIPS ArchitectureBonus Chap. 2 - Instruction Sets*IntroductionThe Instruction Set Architecture is that portion of the machine visible to the assembly level programmer or to the compiler writer.What are the advantages and disadvantages of various instruction set alternatives.How do languages and compilers affect ISA.Use the DLX architecture as an example of a RISC architecture.instruction setsoftwarehardwareChap. 2 - Instruction Sets*Classifying Instruction Set ArchitecturesClassifications can be by:Stack/accumulator/registerNumber of memory operands.Number of total operands.2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture Chap. 2 - Instruction Sets*Instruction Set ArchitecturesAccumulator: 1 address add A acc ¬ acc + mem[A] 1+x address addx A acc ¬ acc + mem[A + x]Stack: 0 address add tos ¬ tos + nextGeneral Purpose Register: 2 address add A B EA(A) ¬ EA(A) + EA(B) 3 address add A B C EA(A) ¬ EA(B) + EA(C)Load/Store: 0 Memory load R1, Mem1 load R2, Mem2 add R1, R2 1 Memory add R1, Mem2Basic ISA ClassesALU Instructions can have two or three operands.ALU Instructions can have 0, 1, 2, 3 operands. Shown here are cases of 0 and 1.Chap. 2 - Instruction Sets*Instruction Set ArchitecturesBasic ISA ClassesStackAccumulatorRegister(Register-memory)Register(load-store)Push ALoad ALoad R1, ALoad R1, APush BAdd BAdd R1, BLoad R2, BAddStore CStore C, R1Add R3, R1, R2Pop CStore C, R3The results of different address classes is easiest to see with the examples here, all of which implement the sequences for C = A + B.Registers are the class that won out. The more registers on the CPU, the better.Chap. 2 - Instruction Sets*Instruction Set ArchitecturesIntel 80x86 Integer RegistersGPR0EAXAccumulatorGPR1ECXCount register, string, loopGPR2EDXData Register; multiply, divideGPR3EBXBase Address RegisterGPR4ESPStack PointerGPR5EBPBase Pointer – for base of stack seg.GPR6ESIIndex RegisterGPR7EDIIndex RegisterCSCode Segment PointerSSStack Segment PointerDSData Segment PointerESExtra Data Segment PointerFSData Seg. 2GSData Seg. 3PCEIPInstruction CounterEflagsCondition CodesChap. 2 - Instruction Sets*Memory AddressingSections Include:Interpreting Memory AddressesAddressing ModesDisplacement Address ModeImmediate Address Mode2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture Chap. 2 - Instruction Sets*Memory AddressingWhat object is accessed as a function of the address and length?Objects have byte addresses – an address refers to the number of bytes counted from the beginning of memory.Little Endian – puts the byte whose address is xx00 at the least significant position in the word.Big Endian – puts the byte whose address is xx00 at the most significant position in the word.Alignment – data must be aligned on a boundary equal to its size. Misalignment typically results in an alignment fault that must be handled by the Operating System.Interpreting Memory AddressesChap. 2 - Instruction Sets*Memory AddressingAddressing ModesThis table shows the most common modes. A more complete set is in Figure 2.6Addressing ModeExample InstructionMeaningWhen UsedRegisterAdd R4, R3R[R4] 17 )goto AddrAt Assembler level:Load R2, 3Add R0, R1, R2Load R2, 17CMPBGT R1, R2Load R1, AddressJump (R1)Chap. 2 - Instruction Sets*Operations In The Instruction SetSections Include:Detailed information about types of instructions.Instructions for Control Flow (conditional branches, jumps)2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture Chap. 2 - Instruction Sets*Operations In The Instruction SetArithmetic and logical ­ and, add Data transfer ­ move, load Control ­ branch, jump, call System ­ system call, traps Floating point ­ add, mul, div, sqrt Decimal ­ add, convert String ­ move, compare Multimedia - 2D, 3D? e.g., Intel MMX and Sun VIS Operator TypesChap. 2 - Instruction Sets*Operations In The Instruction SetControl Instructions Issues:taken or notwhere is the target link return addresssave or restore Instructions that change the PC:(conditional) branches, (unconditional) jumpsfunction calls, function returnssystem calls, system returnsControl InstructionsConditional branches are 20% of all instructions!!Chap. 2 - Instruction Sets*Operations In The Instruction SetThere are numerous tradeoffs:Compare and branch + no extra compare, no state passed between instructions -- requires ALU op, restricts code scheduling opportunities Implicitly set condition codes ­ Z, N, V, C + can be set ``for free'' -- constrains code reordering, extra state to save/restore Explicitly set condition codes + can be set ``for free'', decouples branch/fetch from pipeline -- extra state to save/restore Control InstructionsThere are numerous tradeoffs:condition in general­purpose register + no special state but uses up a register -- branch condition separate from branch logic in pipeline some data for MIPS > 80% branches use immediate data, > 80% of those zero 50% branches use == 0 or 0 compromise in MIPS branch==0, branch0 compare instructions for all other compares Chap. 2 - Instruction Sets*Operations In The Instruction SetLink Return Address:implicit register ­ many recent architectures use this + fast, simple -- s/w save register before next call, surprise traps? explicit register + may avoid saving register -- register must be specified processor stack + recursion direct -- complex instructions Control InstructionsSave or restore state:What state? function calls: registers system calls: registers, flags, PC, PSW, etc Hardware need not save registers Caller can save registers in use Callee save registers it will use Hardware register save IBM STM, VAX CALLS Faster? Many recent architectures do no register saving Or do implicit register saving with register windows (SPARC) Chap. 2 - Instruction Sets*Type And Size of OperandsThe type of the operand is usually encoded in the Opcode – a LDW implies loading of a word.Common sizes are:Character (1 byte)Half word (16 bits)Word (32 bits)Single Precision Floating Point (1 Word)Double Precision Floating Point (2 Words)Integers are two’s complement binary.Floating point is IEEE 754.Some languages (like COBOL) use packed decimal.2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture Chap. 2 - Instruction Sets*Encoding And Instruction SetThis section has to do with how an assembly level instruction is encoded into binary.Ultimately, it’s the binary that is read and interpreted by the machine.2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture We will be using the Intel instruction set which is defined at: 2 has the instruction set.Chap. 2 - Instruction Sets*Encoding And Instruction Set80x86 Instruction Encodingfor ( index = 0; index : add $0x10,%esp0x8048532 : lea 0xfffffff8(%ebp),%edx0x8048535 : test %esi,%esi0x8048537 : jle 0x8048543 0x8048539 : mov %esi,%eax0x804853b : nop0x804853c : lea 0x0(%esi,1),%esi long_temp = (*alignment + long_temp) % 47;0x8048540 : dec %eax0x8048541 : jne 0x8048540 0x8048543 : add $0xfffffff4,%espHere’s some sample code that’s been disassembled. It was compiled with optimizationThis code was produced using gcc and gdb.For details, see Lab 2.1Note that the representation of the code is dependent on the compiler/debugger!Chap. 2 - Instruction Sets*Encoding And Instruction Set80x86 Instruction EncodingRegADDDisp.348postbyteSHL68V/w2Disp.8TEST7W1postbyte8Immediate8W1A Morass of disjoint encoding!!This is Figure D.8Chap. 2 - Instruction Sets*Encoding And Instruction Set80x86 Instruction EncodingCALLFOffsetSegment NumberCondJEDisp.44816168postbyteMOV68D/w2Disp.8PUSH5Reg3Chap. 2 - Instruction Sets*Encoding And Instruction Set80x86 Instruction EncodingC7 /0 MOV r/m32,imm32 Move an immediate 32 bit data item to a register or to memory.Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, general purpose register, segment register, or memory location. Both operands must be the same size, which can be a byte, a word, or a doubleword.In our case, because of the “C7” Opcode, we know it’s a sub-flavor of MOV putting an immediate value into memory.Here’s the instruction that we had several pages ago:0040D3AF C7 45 F0 00 00 00 00 mov dword ptr [ebp-10h],0Is described in: found it on page 479, but this is obviously version dependent.)C7 45 F0 00 00 00 00 mov dword ptr [ebp-10h],0Op Code forMov Immediate32 bits of 0.Target Register+ use next 8 bits as displacement.This is-10 hex.Chap. 2 - Instruction Sets*The Role of CompilersCompiler goals: All correct programs execute correctly Most compiled programs execute fast (optimizations) Fast compilation Debugging support 2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture Chap. 2 - Instruction Sets*The Role of CompilersSteps In CompilationParsing ­­> intermediate representation Jump Optimization Loop Optimizations Register Allocation Code Generation ­­> assembly code Common Sub­Expression Procedure in-lining Constant Propagation Strength Reduction Pipeline Scheduling Chap. 2 - Instruction Sets*The Role of CompilersSteps In CompilationOptimization NameExplanation% of the total number of optimizing transformationsHigh LevelAt or near the source level; machine-independentNot MeasuredLocalWithin Straight Line Code40%GlobalAcross A Branch42%Machine DependentDepends on Machine KnowledgeNot MeasuredChap. 2 - Instruction Sets*The Role of CompilersWhat compiler writers want:regularity orthogonality composability Compilers perform a giant case analysis too many choices make it hard Orthogonal instruction sets operation, addressing mode, data type One solution or all possible solutions 2 branch conditions ­ eq, lt or all six ­ eq, ne, lt, gt, le, ge not 3 or 4 There are advantages to having instructions that are primitives.Let the compiler put the instructions together to make more complex sequences.Chap. 2 - Instruction Sets*The MIPS ArchitectureMIPS is very RISC oriented.MIPS will be used for many examples throughout the course.2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The MIPS Architecture Chap. 2 - Instruction Sets*The MIPS ArchitectureMIPS CharacteristicsThere’s MIPS – 32 that we learned in CS140 32­bit byte addresses aligned Load/store ­ only displacement addressing Standard datatypes 3 fixed length formats 32 32­bit GPRs (r0 = 0) 16 64­bit (32 32­bit) FPRs FP status register No Condition Codes Data transfer load/store word, load/store byte/halfword signed? load/store FP single/double moves between GPRs and FPRs ALU add/subtract signed? immediate? multiply/divide signed? and,or,xor immediate?, shifts: ll, rl, ra immediate? sets immediate? There’s MIPS – 64 – the current arch.Standard datatypes 4 fixed length formats (8,16,32,64)32 64­bit GPRs (r0 = 0) 64 64­bit FPRs Addressing ModesImmediateDisplacement (Register Mode used only for ALU)Chap. 2 - Instruction Sets*The MIPS ArchitectureMIPS CharacteristicsControl branches == 0, 0 conditional branch testing FP bit jump, jump register jump & link, jump & link register trap, return­from­exception Floating Pointadd/sub/mul/div single/double fp converts, fp set Chap. 2 - Instruction Sets*The MIPS ArchitectureThe MIPS EncodingOp312601516202125Rs1RdimmediateOp3126025Op312601516202125Rs1Rs2targetRdOpxRegister-Register561011Register-ImmediateOp312601516202125Rs1Rs2/OpximmediateBranchJump / CallChap. 2 - Instruction Sets*BONUScombines 3 features architecture implementation compilers and OS argues that implementation effects are second order compilers are similar RISCs are better than CISCs: fair comparison? RISC versus CISCChap. 2 - Instruction Sets*BONUSRISC factor: {CPI VAX * Instr VAX }/ {CPI MIPS * Instr MIPS } Benchmark Instruction CPI CPI CPI RISC Ratio MIPS VAX Ratio factorli 1.6 1.1 6.5 6.0 3.7 eqntott 1.1 1.3 4.4 3.5 3.3 fpppp 2.9 1.5 15.2 10.5 2.7 tomcatv 2.9 2.1 17.5 8.2 2.9 RISC versus CISCChap. 2 - Instruction Sets*BONUSCompensating factors Increase VAX CPI but decrease VAX instruction count Increase MIPS instruction count e.g. 1: loads/stores versus operand specifiers e.g. 2: necessary complex instructions: loop branches Factors favoring VAX Big immediate values Not­taken branches incur no delay RISC versus CISCFactors favoring MIPS Operand specifier decoding Number of registers Separate floating point unit Simple branches/jumps (lower latency) No complex instructions Instruction scheduling Translation buffer Branch displacement size Chap. 2 - Instruction Sets*Wrapup2.1 Introduction 2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing 2.4 Operations in the Instruction Set 2.5 Type and Size of Operands 2.6 Encoding and Instruction Set 2.7 The Role of Compilers 2.8 The DLX Architecture Bonus