Kiến trúc hệ vi xử ký máy vi tính

P&I-Ch1:Architecture 1 Ch.1 Kiến trúc hệ VXL – MT ƒ Kiến trúc thiết bị hệ kinh điển, các hệ nhúng ƒ Kiến trúc hệmáy tính ‘Hi Performance’ - desktop ƒ Hoạt động của hệ thống. P&I-Ch1:Architecture 2 1.1. Kiến trúc Hệ VXL, Máy tính kinh điển – Embedded systems 1.1.1. Sơ đồ: 3 phần: - CS, - Ngoại vi & - Interface P&I-Ch1:Architecture 3 1.1.1. a. Central Sub System – CS: + CPU: Central Processing Unit: • Khái niệm: Là bộ điều khiển trung tâm, thực hiện công việc được giao đặt trong bộ nhớ chương trình bằng cách thực hiện các phép xử lý lên các biến nhị phân và điều khiển thiết bị ngoại vi. • Công việc bao gồm: – Tìm lệnh, giải mã lệnh, [tìm toán hạng, xử lý và cất kết quả], – In/Out với các port kiểu Interrupt và DMA để điều khiển thiết bị ngoại vi. P&I-Ch1:Architecture 4 ¾Đặc trưng – Specifications: • Kích thước toán hạng (bit): 4, 8, 12, 16, 32, 64... • Tốc độ xử lý: Mips, clock multiplier, • Kiến trúc: – RISC (Reduced Instruction Set Computer)vs CISC (Complex Instruction Set Computer), – DSP – Digital Signal Processor, – Micro Controller (All in one) • Pinning/Signalling (Data/Address - Mux, Control bus, IRQ, HRQ, RD/WR...), • Register set, • Instruction set – Addressing Modes, • Power: Slow/ sleep/ power down modes • ... P&I-Ch1:Architecture 5 + Memories (Semiconductor): K/n & ROM: Khái niệm: • Lưu thông tin (ch/tr và số liệu) dạng nhị phân, • Dung lượng lớn (upto 100s Mega bit), tốc độ truy nhập nhanh (downto ns access time). – Physically: tính chất vật lý như thế nào? • ROMs: Mask ROM, PROM, EPROM, EAROM, OTROM, NonVolatile mem, ... • Là bộ nhớ chỉ đọc, vẫn lưu thông tin khi mất điện, • Package : byte • Access time:100..120ns • Ghi/nạp nội dung: T/bị chuyên dùng (ROM Burner /Programmator) • Shadow ROM?: copy nội dung từ ROM sang DRAM mỗi khi khởi động P&I-Ch1:Architecture 6 Memories (Semiconductor): SRAM ¾ L−u th«ng tin t¹m thêi, kh«ng l−u ®−îc khi mÊt ®iÖn, ®äc vµ ghi ®−îc, [Read/Write Mem]. ¾Static RAM: ¾ nhanh (80..3 ns), ¾ byte/nibble package, ¾ mËt ®é byte/chip nhá (upto 64/256 KB/ chip), ¾ ®¾t, tiªu thô c«ng suÊt nhiÒu, ¾ CMOS RAM: chËm vµ tiªu thô cùc Ýt, less μW. Vdô: MC 146818 RealTimeClock-CMOS RAM ¾ Dïng trong c¸c hÖ nhá, cache memory. P&I-Ch1:Architecture 7 Memories (Semiconductor): DRAM Dynamic RAM: DRAM: ƒ Tèc ®é/Access time (50-70ns), [10..20ns] Pre-fetched ƒ MËt ®é bit/chip >> (1 Gbit/chip – 1996, Korea), ƒ bit package => DRAM bank, ƒ Tiªu thô c«ng suÊt nhá. ƒ Th«ng tin chØ l−u ®−îc 10ms => refreshing DRAM víi chu kú @ 7,5ms => phøc t¹p. ƒ Dïng trong c¸c hệ cã dung l−îng nhí lín: m¸y tÝnh, m¸y chñ... P&I-Ch1:Architecture 8 Memories (Semiconductor): FLASH & Others Flash memory: EAROM typed, ®äc ®−îc, xo¸ tõng bank, ghi l¹i ®−îc tõng byte. Th«ng tin l−u ®−îc 20 năm, dïng nhiÒu hiÖn tại vµ t−¬ng lai: BIOS, diskchip, USB stick Mem... Serial EAROM/FLASH: dïng ®Ó l−u configuration, dïng bus I2C (Philips). VÝ dô øng dông : thÎ vi m¹ch, TV, ... Dual [Quad] Ported RAM: Switching Sys., PGA RAM-DAC: VGA, VoiceChip PCMCIA .... P&I-Ch1:Architecture 9 Memories (Semiconductor): Logically: Bé nhí chøa th«ng tin gì? ƒ Program memory: ƒ chøa ch/tr ®ang ®−îc thùc hiÖn ƒ Data memory: ƒ c¸c biÕn ngÉu nhiªn, ƒ biÕn cã cÊu tróc, ƒ sè liÖu cã kiÓu truy nhËp ®Æc biÖt FIFO, LIFO (Stack memory). P&I-Ch1:Architecture 10 + Controllers: [Optional], vi m¹ch, n©ng hiÖu nang (performance) hÖ thèng, bao gåm: • Bé ®iÒu khiÓn −u tiªn ng¾t PIC – Priority Interrupt Controller, Intel 8259A ƒ Bé ®iÒu khiÓn truy nhËp trùc tiÕp bé nhí DMAC – Direct memory Access Controller, Intel 8237A. ƒ Timer: m¹ch t¹o c¸c kho¶ng thêi gian, PIT- Programmable Interval Timer, Intel 8254. ƒ M¹ch qu¶n trÞ nhí: MMU- Memory Management Unit, sau nµy, th−êng ®−îc built on chip víi CPU. ƒ Bus controller/Arbitor ƒ ... P&I-Ch1:Architecture 11 • PCB (Printed Circuit Board)/ Cable (Twisted pairs, flat..), slot, connector... dïng ®Ó chuyÓn thong tin vµ n¨ng l−îng. • Nèi h¬n 1 slave/master device, time sharing (dïng chung) • Th«ng tin: Address, data, control, status, Power Supply • ChiÒu (dir), 3 state (Hi Z), Loading ADDRESS BUS: – Tõ c¸c BusMaster (CPU, DMAC, PCI host Controller) ®Õn SlaveDevices (Mem, Ports) ®Ó chän/ chá tõng IO/ Mem location trong tõng chu kú bus – n Addr bit Î 2n Mem Locations & 2m IO Locations, m<n + System Bus: K/n & Addr bus P&I-Ch1:Architecture 12 System Bus : Data bus ƒ Data bus: ƒ Sè bit (th−êng) phï hîp víi kÝch th−íc ALU (8/16/32/64 bit) ƒ ChuyÓn Op-code (m∙ lÖnh) trong chu kú m¸y M1, - CPU <= Program Memory, trong c¸c bus cycle M1 ƒ VËn chuyÓn data: - CPU Data memory, - CPU IO Ports vµ - Data Memory IO Ports, DMA P&I-Ch1:Architecture 13 System Bus : Control/Status bus: ƒ gåm c¸c tÝn hiÖu – control bus: ƒ Control/ Response: CPU to Others (MEMR, MEMW, IOR, IOW, INTA, HLDA, BHE...), from CPU ƒ Status/Request to CPU: IRQ, HRQ, Ready, ... to CPU P&I-Ch1:Architecture 14 System Bus: Power Supply: +5V ±5%, 10 ®Õn 20 Amp, cÊp cho c¸c Vi m¹ch sè, RedWire. (3.3V and less) ƒ Ground, Gnd, 0V, signal reference ground, chassis, BlackWire. ƒ +12V ±10%, 1Amp, cÊp cho c¸c m¹ch analog, motors, RS232, YellowWire. ƒ -12V ± 10%, 1Amp, (nh− trªn), BlueWire. ƒ - 5 V±5%, 0.5 Amp, analog circuitries, WhiteWire. ƒ Power good: OrangeWire. ƒ Nguån th«ng minh: AXT P&I-Ch1:Architecture 15 1.1.1.b. ThiÕt bÞ Ngo¹i vi: Input, Output vµ dada Storage devices Data Input Devices: - Key board/ Key pad, Touch SCR: sè phÝm, c«ng nghÖ phÝm, kiÓu dß phÝm, output code, ghÐp nèi CS - Mouse, track ball - Scanner, Camera, Camcoder Optical Mouse, BarCode reader: Colors, resolution, f, c«ng nghÖ CCD - Charge Couple Device, graphics file bit map - bmp. - Digitizer, nhËp graphics file vector - b¶n ®å - Light Pen, Joy stick (Games) - Demodulator (MODEM): Gi¶i ®iÒu chÕ KiÓu ®iÒu chÕ, tèc ®é bps, kiÓu nÐn - Microphone, - Reader: RFID Radio Frequency Identification, Finger print - Laser/ LED - Sensor, Transducers, Transmitters: VËt liÖu, thiÕt bÞ,.. biÕn ®æi c¸c ®¹i l−îng vËt lý - kh«ng ®iÖn, thµnh tin shiÖu ®iÖn ®é nhËy, ®é tuyÕn tÝnh, d¶i ®o... P&I-Ch1:Architecture 16 1.1.1.B. T/bÞ Ngo¹i vi: Data Output Devices: - Displays: KiÓu hiÓn thÞ: Point/ 7Seg/ Text/ Graphics; Mono Chrome/Color (color numbers); Size, indoor/outdoor, Resolution, Rate of Refreshing... - C«ng nghÖ: - LED (Light Emitting Diodes): point, 7(16) Segment, Matrix character box (Bill Board), Outdoor LED Screen... - Organic LED, - LCD (Liquid Crystal Display): single color, color, active, TFT (thin film transistor - CRT (Cathode Ray Tube). P&I-Ch1:Architecture 17 1.1.1.b. T/bÞ Ngo¹i vi: Data Output Devices: Printers: - Spec: Text-Graphics, Mono-Color, Resolution, ppm – page per minute, Size, Line-PostScript, media... : - Pin Printer, - Jet Printer, - Laser Printer, - Thermal Transfer Printer, barcode Printer. - High Speed Text Printer, - ... P&I-Ch1:Architecture 18 1.1.1.b. T/bÞ Ngo¹i vi: Data Output Devices: Others - Plotter, jet - Modulator (MODEM), ®iÒu chÕ - Speaker - Actuator: Motor (dc/ac, Step), Relay, Valve, P&I-Ch1:Architecture 19 1.1.1.b. T/bÞ Ngo¹i vi: Massive Storages: - Magnetic devices: FDD, HDD, RAID, Tape backup drive... - Optical devices: CD [Writer] Drives, Magnetic Optic disk drive... - Semiconductor devices: FlashChip, PCMCIA Card... - Tèc ®é truy nhËp cao, dung l−îng lín P&I-Ch1:Architecture 20 1.1.1.c. Interface: Lý do cÇn interface: kh¸c nhau gi−a CS vµ wide world: – Møc tÝn hiÖu (dßng, ¸p, analog ... ), kiÓu biÓu diÔn tin tøc (nhiÖt ®é, ¸p suÊt, level... Ù bit) – Tèc ®é lµm viÖc/tèc ®é trao ®æi sè liÖu, – Kh«ng ®ång bé... Nªn cÇn cã m¹ch ®iÖn tö ®Ó thÝch øng (Adapting - ports) vµ ch/tr ®iÒu khiÓn, gåm: – ThiÕt bÞ (Hardware Circuitries - Adaptors): cæng IO: • Input/Output Ports: (Parallel/Serial): ghep nối víi Computerized devices PPP (KB, Printer, Mouse, Scanner, Modem, camera,... dïng VXL ®a nang) • Controllers: thùc chÊt lµ nh−ng hÖ VXL chuyªn dïng - ®Ó ghÐp nèi víi nhung thiÕt bÞ chuyªn dïng FDC, HDC (IDE, EIDE), CRTC (EGA, VGA, SVGA...) • Converter: ®Ó chuyÓn ®æi tÝn hiÖu sè thµnh t−¬ng tù vµ ng−îc l¹i: ADC, DAC – vÝ dô sound card P&I-Ch1:Architecture 21 IO buses: • Expansion bus, IO bus, IO system, ... • ISA, EISA, MC, PCI, USB, IEEE 1394, SSA, IEEE 488 ... P&I-Ch1:Architecture 22 1.1.1.c. Interface: Ch/tr ®iÒu khiÓn – Device Driver: - K/n: Hardware or Software? + Software: s¶n phÈm cña NN lËp trinh + Hardware: lu«n gan liÒn víi IO hardware • Liªn kÕt System Programs and/or Application Programs víi IO hardware (SPIs vµ APIs). • C¸c hµm cña thiÕt bÞ, BIOS, OS hoÆc theo øng dông: SLLs, DLLs, DRVs, ... • HiÖn 1 x©u ký tù: mov ah,9 mov ah,0 mov dx,offset xau int 16h ; BIOS same int 21h mov ah,1 int 21h P&I-Ch1:Architecture 23 Case study PC layers Fig. 1b: PC’s Layers (IBM PC Institute) P&I-Ch1:Architecture 24 1.1.2. kiÕn tróc m¸y tÝnh hiÖu n¨ng cao hi performance architecture (server, desktop, laptop) P&I-Ch1:Architecture 25 1.1.2. Hi-Per. Architecture:1.1.2.a. Local Buses: VÝ dô VESA VL-Bus 2.0 [late 1993], Memory [1985]. Also called system/host/processor bus. ChØ liªn kÕt CPU, MMU (gåm Cache, DRAM, shadowed ROM ) vµ PCI Host [Bridge], Ýt, gÇn, unbuffered (direct connected to Processor); 33, 66, 100, 133, 200, 400, 800 MHz... clock. 32 bit A/D (16 bit support also), burst mode, max 132 MBps, Addr D0 D1 D2 D3 D4 (data 4 byte) H.1.3. VÝ dô burst mode: P&I-Ch1:Architecture 26 1.1.2. Hi-Per Architecture:1.1.2.b. Hi Speed Bus: - Peripheral Component Interconnect - PCI - 5/1993, Intel Ver. 2.0, Open Standard, - Local bus, møc trung gian gi÷a Local vµ c¸c bus chuÈn kh¸c (ISA, MC, EISA) th«ng qua PIC Bridge/Controller. - Cã kiÓm tra parity cho Addr vµ Data - Auto configuration of all PCI devices, share the same IRQ. Disabling IRQ => cÊm toµn bé PCI devices. - No DMA, device on PCI bus lµ bus master (Tèt cho viÖc dïng MultiTasking OS). - Burst mode: 32 bit @33MHz --> 96..132MBps, tuú thuéc sè byte (tõ 32 byte ®Õn 4KB). Option 64bit @33MHz --> 264MBps - Most Platforms use:Intel, DEC Alpha, PowerPC, Spark - Modern OS: ‘Block Typed Devices’: tÇn suÊt vËn chuyÓn cao, nhanh, data block P&I-Ch1:Architecture 27 1.1.2. Hi-Per Architecture:1.1.2.c. Expansion Bus: - So called: standard buses, expansion bus, slots, IO bus, IO system, channel bus): ISA, EISA, MC... - MC bus: 32 bit, 10MHz, 20..40MBps, 15 BusMaster, Auto config, 1987, IBM - EISA bus: 32 bit, 8,33 MHz, 33MBps, 4 BMs, AutoConfig (EISA card only), 1989, Compaq - ISA (Industry Small Architecture), AT bus: - Spec. 8/16 bit (data), 8MHz..11MHz, 5..5 MBps max, 1Bus Master, no PnP, 1984, IBM. - RÊt phæ biÕn, cßn tån t¹i l©u, Espec. @ iPC, - H¹n chÕ sè IRQs, 4 DRQs, - Dïng DIP switch/jumper ®Ó config. - No data integrity features (no party checking) - Modern OS: ‘Character Typed Devices’ P&I-Ch1:Architecture 28 1.2. Ho¹t ®éng cña hÖ thèng: ƒ Reset, ƒ Opcode fetch and Execute, ƒ Interrupt, ƒ DMA - halt & ƒ Ready (wait state - ws) P&I-Ch1:Architecture 29 1.2. Ho¹t ®éng cña hÖ thèng:1.2.1. L−u ®å tæng qu¸t: reset ProgCounter = ResetAddr/vector DMA? IRQ? DMA? Machine On Halt OpCode Fetch OpCodeDecode Execute PC = Intr. Vector MaskOn n n n n H×nh 1.3. L−u ®å tæng qu¸t cña VXL (Motorola), Training courses y y y y y P&I-Ch1:Architecture 30 1.2. Ho¹t ®éng cña hÖ thèng: 1.2.2. Reset : • Cold Start: BÊm nót reset/Power-On =>Xo¸ tr¹ng th¸i hiÖn hµnh, cÊm ng¾t, DMA. CPU ®−îc khëi t¹o (PC- Program Counter (hoÆc CS:IP), Flags vµ SP...). C¸c thiÕt bÞ trong hÖ cïng ®−îc reset. (Sau khi reset, CPU sÏ tim vμ t/h lÖnh – víi c¸c thñ tôc sau) • Warm Start: do lÖnh gäi, (Int 19h, Ctrl_Alt_Del) • POST (Power On Self Test - ch/tr monitor/ BIOS) ®Ó kiÓm tra mäi thiÕt bÞ theo nguyªn t¾c ghi vµ ®äc l¹i (Registers, RAM) hoÆc ®äc vµ kiÓm tra Check Sum (ROM). • Initializing - khëi t¹o: ®Æt c¸c tham sè => configuring. • [M¸y tÝnh - N¹p hÖ ®iÒu hµnh ]. P&I-Ch1:Architecture 31 1.2.3. DMA: (Xem Ch. 3.2.) 1.2.4. Interrupt: (Xem Ch. 3.3.) P&I-Ch1:Architecture 32 1.2. Ho¹t ®éng cña hÖ thèng: 1.2.5. T×m vµ thùc hiÖn lÖnh : DiÔn ra chñ yÕu trong thêi gian ho¹t ®éng, ngo¹i trõ lÖnh HLT. Ch/tr ng«n ng÷ m¸y: tËp hîp c¸c lÖnh cã cÊu tróc, cã nghÜa, thùc hiÖn 1 thuËt to¸n. Chu kú lÖnh (Instruction Cycle): Kho¶ng thêi gian CPU thùc hiÖn xong 1 lÖnh, gåm: t×m lÖnh, gi¶i m∙ lÖnh, [t×m to¸n h¹ng vμ thùc hiÖn lÖnh (thùc hiÖn c¸c phÐp xö lý hoÆc vμo-ra)]. ®é dµi lÖnh: (CISC)1 hay nhiÒu byte, Thêi gian t/h:(CISC)1/nhiÒu chu kú m¸y (chu kú bus). Chu kú m¸y (Bus/Machine Cycle): thêi gian BusMaster thùc hiÖn thao t¸c trªn bus: ®äc/ghi « nhí hay IO port Clock cycle: Chu kú m¸y: 4..12 chu kú clock, tuú CPU. P&I-Ch1:Architecture 33 1.2. Ho¹t ®éng cña hÖ thèng: Cã 8 CPU’s BusCycles: • M1, opcode fetching, Addr =>Program mem, -MEMR • Data mem Reading, Addr=>Data mem, -MEMR • Data mem Writing, Addr=>Data mem, -MEMW • Input Port Reading, Addr=> IO space, -IOR • Out Port Writing, Addr => IO space, -IOW • Interrupt Acknowledge, -INTA, • Halt, waiting for Ext. Intr. hoÆc reset • Bus Idle Thªm 2 chu kú bus cña DMAC: • IOR-MemW DMA bus cycle vμ • MemR-IOW DMA bus cycle. P&I-Ch1:Architecture 34 1.2. Ho¹t ®éng cña hÖ thèng: 1.2.6. Wait State (Ready): ¾ Th−êng dïng ®Ó ghÐp nèi: bé nhí, ngo¹i vi tèc ®é chËm. ¾ Hoạt động Khi BusMaster ph¸t ®Þa chØ & tÝn hiÖu ®äc/ghi (thªm c¸c tÝn hiÖu kh¸c) ®Ó thùc hiÖn 1 chu kú bus, MMU/IO port [Controller] chñ ®éng ph¸t ra tÝn hiÖu Ready=0 (not Ready) ®Ó yªu cÇu BusMaster gi÷ nguyªn tr¹ng th¸i bus thªm 1 [vµi] nhÞp clock. P&I-Ch1:Architecture 35 Case Study: IOW bus cycles w/o and w 1 wait state: P&I-Ch1:Architecture 36 1.3. Thiết bị ngoại vi: 1.3.1. Key boards: • Khái niệm: – Thiết bị nhập số liệu và ra lệnh cho máy – Phân loại: • Contact keys • Non contact keys • Membrane keys – Technical Problems: • Key bouncing • Ghost keys P&I-Ch1:Architecture 37 • Key organization: matrix • Key polling: – Line reversal technique: (Fig. 1.5) – Scan (Fig. P&I-Ch1:Architecture 38 P&I-Ch1:Architecture 39 P&I-Ch1:Architecture 40 P&I-Ch1:Architecture 41 PC Key board P&I-Ch1:Architecture 42 P&I-Ch1:Architecture 43 P&I-Ch1:Architecture 44 1.3.2. Màn hình P&I-Ch1:Architecture 45 P&I-Ch1:Architecture 46 Bµi tËp ch−¬ng 1 • T×m hiÓu bus ISA (Ch4), thiÕt kÕ mạch logic đÓ chÌn c¸c ws cho ISA slot khi CPU đäc/ ghi 1 ®ịa chỉ cổng • T¹o m¹ch kiÓm tra parity - 74HC280