Investigation of charge traps at Al-Doped hfo2/(100 Ingaas interface by using capacitance and conductance methods - Thoan Nguyen-Hoang

Vietnam Journal of Science and Technology 56 (1A) (2018) 110-118 INVESTIGATION OF CHARGE TRAPS AT Al-DOPED HfO2/(100)InGaAs INTERFACE BY USING CAPACITANCE AND CONDUCTANCE METHODS Thoan Nguyen-Hoang 1, * , Sang Nguyen-Xuan 2 , Trung Nguyen-Ngoc 1 1 School of Engineering Physics, Hanoi University of Science and Technology, N o . 1 Dai Co Viet road, Ha Noi, Viet Nam 2 Low Energy Electronic Systems IRG (LEES), Singapore-MIT Alliance for Research and Technology, 1 CREATE Way, Singapore 138602, Singapore * Email: thoan.nguyenhoang@hust.edu.vn Received: 11 August 2017; Accepted for publication: 21 March 2018 ABSTRACT In this study, capacitance and conductance methods were used to investigate the charge traps at a HfO2/(100)InGaAs interface with an atomic layer deposition HfO2 layer doped with Al2O3 by co-deposition technique. The effect of Al doping on the quality of the HfO2/In0.53Ga0.47As interface will be evaluated. The density of interface traps (Dit) near In0.53Ga0.47As midgap is close to 2×10 12 cm −2 eV −1 . Based on comparison to the HfO2/In0.53Ga0.47As interface without Al2O3 interfacial passivation where the value Dit∼10 13 cm −2 eV −1 is encountered near the midgap, we can conclude that the presence of Al2O3 passivation noticeably improves the interface quality. Keywords: HfO2, InGaAs, interface traps, capacitance method, conductance method. 1. INTRODUCTION III-V channel materials are expected to replace Si for nMOSFET components due to their very high electron mobility. It has already been demonstrated that ultra-high mobility compound semiconductor-based MOSFETs and quantum well FETs (e.g., In0.7Ga0.3As and InSb) [1, 2] operate at low VSD with high performance. Furthermore, In0.7Ga0.3As MOSHEMTs with an InP barrier stack have been demonstrated with 3.5 times higher effective carrier velocity than strained-Si n-MOSFETs [3]. In addition, another advantage of III-V semiconductors is their direct bandgap raising much interest for optical and photonic device application. However, the most important issue in III-V technology still concerns the semiconductor surface passivation, Surface passivation of III-V materials has been extensively investigated in the past few decades and it is still a very active topic especially regarding MOSFET structures. III-V semiconductors lack wide bandgap insulating native oxides to passivate their interfaces. Therefore, non-native high- oxides represent the natural choice of dielectric materials for application in III-V MOS devices. Fabrication of a high-quality, Investigation of charge traps at Al-doped HfO2/(100)InGaAs interface 111 thermodynamically stable gate dielectric that can passivate the III-V semiconductor interfaces efficiently remains the key challenge for III-V MOSFET technology. Atomic layer deposition (ALD)-hafnium dioxide is considered as a potential gate oxide for III-V MOSFET devices. HfO2 is considered as a leading candidate for high-κ dielectric devices because of its high dielectric constant and good thermal stability in comparision to other oxide materials. The HfO2 dielectric with κ 20 has been successfully applied to 45-nm silicon MOSFET devices [4, 5]. However, the deposition of pure HfO2 directly on In0.53Ga0.47As leads to a poor interface with considerably high density of interface traps (Dit) in the order of 10 13 cm −2 eV −1 closed to the In0.53Ga0.47As midgap [6–8]. Recently, the reduction of Dit was achieved by sulfur pretreatment of the In0.53Ga0.47As surface prior to ALD process of HfO2 [9]. However, native oxides (Ga2O3, In2O3 and As2O3) rapidly regrew upon exposure of the devices to the air resulting in interface degradation. It has been shown that ALD of Al2O3 from the tri-methyl- aluminum (TMA) Al(CH3)3 precursor has a shelf-cleaning effect which is reported to reduce or even remove III-V native oxides [10–12]. However, by itself Al2O3 has a low κ-value (κ ~8) that limits the EOT (equivalent oxide thickness) scaling potential. One may consider using a higher-κ dielectric on III-V in combination with ALD Al2O3 passivation. In this study, we will evaluate the effect of Al doping of the HfO2 dielectric on the quality of the In0.53Ga0.47As/HfO2 interfaces. The electrical characteristics of an electronic device which employs a semiconductor/oxide interface are very sensitive to the interface state density and its distribution in the semiconductor bandgap [13]. Interface charge traps, also called interface states are attributed to the presence of native defects, impurities or damage-related imperfections, e.g., broken bonds, at semiconductor/insulator interfaces. The interface charge traps can be characterized by using several quatities such as Qit, Nit and Dit [14] where Qit is the interface-trapped charge per unit area caused by trapping of electrons or holes by defects at a semiconductor/insulator interface; Nit=(+/-)Qit/q is the number of traps per unit area; and Dit is the energy distribution of Nit inside the semiconductor bandgap which could be calculated as followed: Dit(E) = dNit(E)/dE (1) where E is energy position inside the semiconductor bandgap. Figure 1. Band diagrams of a p-type semiconductor surface region illustrating the presence of interface traps, i.e., acceptor traps “A” and donor traps “D”, inside the semiconduction bandgap at flatband (a), when bending up (b), and when bending down (c). Electron-occupied interface traps are indicated by the bold em dashes and unoccupied traps by the light em dashes [15]. Interface traps are electrically active defects with an energy level distribution throughout the semiconductor bandgap (Figure 1). They may act as generation-recombination centers which could contribute to leakage current, low frequency noise, and reduce carrier mobility in semiconductor. The occupancy of interface traps is determined by the position of their energy levels with respect to the Fermi level at the semiconductor interface: All interface traps below EF Thoan Nguyen-Hoang, Sang Nguyen-Xuan, Trung Nguyen-Ngoc 112 are ocuppied by an electron; however above EF, the traps are empty. Therefore, Qit depends on the semiconductor band bending. There are several experimental methods used to investigate the properties of charge traps at semiconductor/insulator interfaces in metal-oxide-semiconductor (MOS) structures, such as capacitance and conductance methods [13,15,16], the charge pumping method using MOSFETs [17], electron spin resonance (ESR) [18,19], and saturation photovoltage (SPV) technique [20]. Among them, capacitance and conductance methods are the most common ones because of the simplicity of MOS capacitor fabrication. 2. EXPERIMENTAL The studied MOS samples were Ni/Al:HfO2/In0.53Ga0.47As/InP/Cr-Au entities with structure schematically illustrated in Figure 2. The substrates were 300-nm or 200-nm thick As-capped In0.53Ga0.47As films grown by molecular beam epitaxial (MBE) technique on (100)InP wafers. The In0.53Ga0.47As layers were n-type (Si-doped 1×10 17 cm −3 ) or p-type (Be-doped: 1×10 17 cm −3 ) on n + - or p + -InP, respectively. Al-doped HfO2 layers were deposited by chemical beam co- deposition technique from TMA and hafnium tertbutoxide at 400 o C, as detailed in Ref. [21], resulting in a thickness of ∼5 nm. After oxide deposition, the samples were annealed at 400 oC in nitrogen. MOS structures were completed with 80-nm thick Ni metal gates, with an area of (1–4)×10−4 cm2, by electron beam evaporation through a shadow mask, and with back ohmic contacts of Cr(10 nm)/Au(100 nm). To extract energy distribution of interface trap Dit(E), capacitance-voltage (CV) and conductance-voltage (GV) measurements were performed at different temperatures from 300 K to 77 K (in liquid nitrogen), in the frequency range 10 2–106 Hz by using a HP4192A impedance analyzer. For the n-type In0.53Ga0.47As substrate, it was proved that this temperature range was sufficient to cover most trap energy levels in the upper half bandgap of In0.53Ga0.47As [22]. The Dit(E) across the In0.53Ga0.47As bandgap was extracted using low frequency capacitance, high- low frequency capacitance and conductance methods [13]. To determine the energy scale for the interface trap density distribution, it is critical to know the semiconductor surface band bending s as a function of the gate bias VG [23], which can be extracted from low frequency CV curves (CLF). The surface band bending can be found Figure 2. Structures of studied In0.53Ga0.47As/HfO2 MOS capacitors, where the oxide layers were Al-doped with the aim to passivate the semiconductor/oxide interfaces. Figure 3. Surface band diagrams of n-type (a), and p-type (b) semiconductors showing how the position of the Fermi level at the semiconductor surface is related to the band bending. The arrows pointing up denote negative potential s, whereas the arrows pointing down denote positive surface potential s. Investigation of charge traps at Al-doped HfO2/(100)InGaAs interface 113 from the low frequency CV measurements through numerical integration (the Berglund integral) [16], in combination with the flatband voltage point (VFB) inferred from a high-frequency CV curve (CHF). First of all, we have the following relation based on the gate charge calculation: ox oxG LF GdQ C dV C dV (2) where QG is the gate charge, Vox is the potential drop across the oxide. So that ox oxLF G dV C C dV . Since oxG sdV dV d , we have ox 1 LFs G C d dV C . Finally, using the definition that surface band bending at flatband voltage is equal to zero, s(VFB) = 0, the following equation is obtained by integrating above equation ox ( ) 1 G FB V LF s G V C V dV C . (3) As the next step, using semiconductor surface band diagrams as shown in Figure 3 and noticing that the trap changes their electron occupancy when crossing the Fermi level, we can associate the energy position E of an interface trap level with the Fermi level at a given s. The position E with respect to the semiconductor valance band edge is given as 2 g V s B E E E q q (4) where, ln DB i NkT q n or ln AB i NkT q n for an n-type and a p-type semiconductor, respectively. These value are obtained from the measured donor and acceptor concentrations, ND and NA, respectively; ni is the intrinsic carrier concentration of the semiconductor (ni = 6.3×10 11 cm −3 for In0.53Ga0.47As at 300 K), s is the surface potential, and Eg is energy bandgap of the semiconductor (Eg=0.737 eV for In0.53Ga0.47As at 300 K). The doping concentrations ND, NA can be extracted from a high-frequency CV curve. The number of interface traps ∆Nit located between the Fermi levels at 300 and 77 K was determined from the flatband voltage shift (∆VFB) on 1-MHz CV curves observed when cooling the sample down from 300 to 77 K. 3. RESULTS AND DISCUSSION Figure 4 shows multi-frequency CV curves measured at 300 K on a p- In0.53Ga0.47As/Al:HfO2/Ni capacitor. We observed a huge frequency dispersion in maximum of capacitance, suggesting an interface trap response. However, in the absence of well behaving CV or GV curves, it is difficult to extract Dit values for this p-type sample. The trapped charge density was evaluated by the hysteresis hysV observed in the CV curves by using the following equation ot ot ox hysQ qN C V (5) where Cox is the oxide capacitance (per unit area). A 0.6V hysteresis observed on this sample indicated a high density of oxide trapped charge, Not ∼(6±1)×10 12 cm −2 . A CV curve hysteresis in Thoan Nguyen-Hoang, Sang Nguyen-Xuan, Trung Nguyen-Ngoc 114 the MOS structure has usually been attributed to the presence of slow traps, that can communicate with the semiconductor substrate by a tunneling process, as extensively discussed by Fleetwood et al. [24]. Figure 5 shows multi-frequency CV curves measured on an In0.53Ga0.47As/Al:HfO2/Ni capacitor at different temperatures in the range from 77 to 300 K. At 300 K, a strong frequency dispersion is observed in the inversion region due to the minority carrier response. In Figure 5(a), we notice presence of a peak in the inversion range. This peak is unlikely to be associated with interface trap response since it is seem to disappear entirely upon cooling the sample to 180 K (Figure 5(b)). At this temperature, one would not expect the response of interface states to be completely eliminated. Figure 5. Multi-frequency CV curves measured at 4 different temperatures in the range 77–300 K on an n-(100)In0.53Ga0.47As/Al:HfO2/Ni capacitor. Figure 4. Multi-frequency CV curves measured at 300 K on a p(100)In0.53Ga0.47As/Al:HfO2/Ni capacitor. Arrows indicate the direction of the voltage sweep. (a) (b) (c) (d) Investigation of charge traps at Al-doped HfO2/(100)InGaAs interface 115 Figure 6 shows the Dit(E) distribution extracted by the high-low frequency CV, low frequency CV, and GV methods. The parameters of In0.53Ga0.47As used for the high-low frequency CV include: the doping concentration ND = 1×10 17 cm −3 , intrinsic concentration ni = 6.3×10 11 cm −3 , dielectric constant s = 12.4 and Debye length λD=0.004 cm. The Cox value was chosen at VG = 2.5 V on the 100-Hz CV curve measured at 300 K. The results obtained from the three Dit evaluation techniques are in good agreement in the midgap range, all close to the value 2×10 12 cm −2 eV −1 . Based on comparison to the In0.53Ga0.47As/HfO2 interface without Al2O3 interface passivation where the value Dit∼10 13 cm −2 eV −1 is encountered near the midgap [25], we can conclude that the presence of Al2O3 passivation noticeably improves the interface quality. A noteworthy observation also in figure 6 is that Dit values near the conduction band edge derived by the CV methods are much higher than the values obtained by the GV method, suggesting a contribution of slow traps to the capacitance response. A 0.2-V hysteresis is observed on the n- type sample which indicates an oxide trapped charge density of Not∼(2±1)×10 12 cm −2 , smaller than the value observed for the p-type sample, Not∼(6±1)×10 12 cm −2 . A portion of the oxide traps near the interface may contribute to the slow traps near the In0.53Ga0.47As CB edge as revealed by the CV method, Figure 6. Figure 7 compares CV curves measured on both p- and n-type In0.53Ga0.47As/Al:HfO2 samples at 300 and 77 K. For the n-type sample, no considerable Gray-Brown shift of VFB was observed when cooling the sample down to 77 K, indicating a low density of interface traps in the energy range close to the In0.53Ga0.47As conduction band edge. From the difference of between VFB values found from 77-K CV curves of n- and p-type samples, the total number of traps Nit can be estimated by using following equation [27, 28]: ox (300 ) / . FB FB g it V n V p E K q N C q (6) where VFB(n) and VFB(p) are flatband voltages of n- and p-type samples, respectively; Eg(300 K) is the semiconductor bandgap at 300 K. In this study, from VFB, the Nit value was estimated to be in order of ∼1×1013 cm−2. This density is much larger than the value of Nit≈2.8×10 12 cm −2 inferred from integration of CV-Dit(E) distribution across the In0.53Ga0.47As bandgap (not Figure 6. Energy distribution of the interface trap density Dit(E) across the In0.53Ga0.47As bandgap at the n-(100)In0.53Ga0.47As/HfO2 interface extracted by the CV and GV methods. Figure 7. 100-kHz CV curves measured at 300 K (solid line) and 77 K (dashed line) on both p- and n-(100)In0.53Ga0.47As/Al:HfO2/Ni capacitors for voltage sweeps from -2.5 to +2.5 V and back. Thoan Nguyen-Hoang, Sang Nguyen-Xuan, Trung Nguyen-Ngoc 116 shown), indicating the presence of slow traps in large density, which is consistent with the observed CV curve hysteresis. 4. CONCLUSION An improved n-In0.53Ga0.47As/HfO2 interface was achieved by Al doping of the HfO2 layer during deposition, resulting in a Dit near midgap close to 2×10 12 cm −2 eV −1 . From this observation, we can conclude that the presence of Al at the In0.53Ga0.47As/HfO2 interface improves the electrical quality of the interface. It may possibly be related with the formation of a very thin Al2O3 interlayer. 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