Digital Logic Design - Lecture 29: Random Access Memory (RAM)

Lecture 29Random Access Memory (RAM)Random Access Memory (RAM) A memory unit is a collection of storage cells together with associated circuits needed to transfer information in and out of the device. Memory cells can be accessed for information transfer to or from any desired random location and hence the name Random Access Memory, abbreviated as RAMOverviewMemory is a collection of storage cells with associated input and output circuitryPossible to read and write cellsRandom access memory (RAM) contains words of informationData accessed using a sequence of signalsLeads to timing waveformsDecoders are an important part of memoriesSelects specific data in the RAMStatic RAM loses values when circuit power is removed.PreliminariesRAMs contain a collection of data bytesA collection of bytes is called a word A sixteen bit word contains two bytesCapacity of RAM device is usually described in bytes (e.g. 16 MB)Write operations write data to specific wordsRead operations read data from specific wordsNote: new notation for OR gateRAM Interface SignalsData input and output lines carry dataMemory contains 2k wordsk address lines select one word out of 2kRead asserted when data to be transferred to outputWrite asserted when data input to be stored Random Access Memory FundamentalsLets consider a simple RAM chip8 words of 2 bytes each (each word is 16 bits)How many address bits do we need?01010000 1110011011001100 1111111100000000 1010101001010110 0011111111111111 0000000000000001 1000000001010101 1100110000000000 11111111wordPick one of 8 locationsDec Binary0 000 1 0012 0103 0114 1005 1016 1107 11116 Data and Input signals____ address signalsEach bit stored in a binary cellRAM SizeIf memory has 2k words, k address bits are needed23 words, 3 address bitsAddress locations are labelled 0 to 2k-1Common subscripts:Kilo – 210Mega – 220Giga - 230Write OperationApply binary address of word to address linesApply data bits to data input linesActivate write inputData output lines unusedRead input signal should be inactiveDelay associated with writeRead OperationApply binary address of word to address linesActivate read inputData input lines unusedWrite input signal should be inactiveDelay associated with readMemory enable used to allow read andwritesMemory Timing – write operationMemory does not use a clockControl signals may be generated on clock edgesCycle time – time needed to write to memoryIf cycle time is 50 ns, 3 clock edges required (T1, T2, T3)Access time indicates time to readAddress indicates locationData valid on Data Output following access timeTiming Waveforms – read operationMultiple clock signals needed for data read in this example* Note ordering of signals (address, mem enable)Comments about Memory Access and TimingMost computers have a central processing unit (CPU)Processor generates control signals, address, and dataValues stored and then read from RAMThe timing of the system is very important. Processor provides data for the cycle time on writesProcessor waits for the access time for readsTypes of Random Access MemoriesStatic random access memory (SRAM)Operates like a collection of latchesOnce value is written, it is guaranteed to remain in the memory as long as power is appliedGenerally expensiveUsed inside processorsDynamic random access memory (DRAM)Generally, simpler internal design than SRAMRequires data to be rewritten (refreshed), otherwise data is lostOften hold larger amount of data than SRAMLonger access times than SRAMUsed as main memory in computer systemsSDRAMSynchronous DRAM, or SDRAM, is one of the most common types of PC memory now.Memory chips are organized into “modules” that are connected to the CPU via a 64-bit (8-byte) bus.Speeds are rated in megahertz: PC66, PC100 and PC133 memory run at 66MHz, 100MHz and 133MHz respectively.The memory bandwidth can be computed by multiplying the number of transfers per second by the size of each transfer.PC100 can transfer up to 800MB per second (100MHz x 8 bytes/cycle).PC133 can get over 1 GB per second.DDR-RAMA newer type of memory is Double Data Rate, or DDR-RAM.It’s very similar to regular SDRAM, except data can be transferred on both the positive and negative clock edges. For 100-133MHz buses, the effective memory speeds appear to be 200-266MHz.This memory is confusingly called PC1600 and PC2100 RAM, because200MHz x 8 bytes/cycle = 1600MB/s266MHz x 8 bytes/cycle = 2100MB/s.DDR-RAM has lower power consumption, using 2.5V instead of 3.3V like SDRAM. This makes it good for notebooks and other mobile devices.RDRAMAnother new type of memory called RDRAM is used in the Playstation 2 as well as some Pentium 4 computers.The data bus is only 16 bits wide.But the memory runs at 400MHz, and data can be transferred on both the positive and negative clock edges.That works out to a maximum transfer rate of 1.6GB per second.You can also implement two “channels” of memory, resulting in up to 3.2GB/s of bandwidth.Binary CellBCSelectOutputInputRead/WriteSelect input enables the cell for reading or writingRead/Write input determines the cell operation when it is selectedMemory CellBCSelectOutputInputRead/WriteBasis of each SRAM cell is an S-R latchNote that data goes to both S and RSelect enables operationRead/write enables read or write, but not bothInside the RAM DeviceAddress inputs go into decoder Only one output activeWord line selects a row of bits (word)Data passes through OR gateEach binary cell (BC) stores one bitInput data stored if Read/Write is 0Output data driven if Read/Write is 1Decoding circuit is required to select the memory word specified by the input addressInside the SRAM DeviceNote: delay primarily depends on the number of wordsDelay not effected by size of wordsHow many address bits would I need for 16 words?WordAnother Configuration (Internal Construction)It consists of 4 words of 3 bits each and has a total of 12 binary cells.A memory with four words needs two address lines. The two address inputs go througha 2 X 4 decoder to select one of the four wordsWhen the memory enable is 0, all outputs of the decoder are 0 and none of the memory words are selectedArray of RAM ChipsIntegrated-circuit RAM chips are available in a variety of sizesIf the memory unit needed for an application is larger than the capacity of one chip, it is necessary to combine a number of chips in an array to form the required memory size.Capacity of the memory depends on two parameters: the number of words and the number of bits per word. An increase in the number of words requires that we increase the address length Every bit added to the length of the address doubles the number of words in memory. The increase in the number of bits per word requires that we increase the length of the data input and output lines, but the address length remains the same.Array of RAM Chips Constructing a 4K x 8 RAM with four 1 K x 8 RAM4K x 8 RAM 1 K x 8 RAMDecoder 00=> 0 to 1023Decoder 01=> next 1024Decoder 10=> next 1024Decoder 11=> next 1024Composite MemoryTwo chips can be combined to form a composite memory containing the same number of words but with twice as many bits in each word.16 input and output data lines are split between the two chips. Both receive the same IO-bit address and the common CS and RW control inputs.Error-Detection and Correcting CodeMemory array may cause occasional errors in storing and retrieving the binary informationReliability of a memory unit may be improved by employing error-detecting and correcting codesError DetectionThe most common error-detection scheme is the parity bitA parity bit is generated and stored along with the data word in memory. The parity of the word is checked after reading it from memory. The data word is accepted if the parity sense is correct. If the parity checked results in an inversion, an error is detected, but it cannot be corrected.Error-Detection and Correcting CodeError CorrectionAn error-correcting code generates multiple check bits that are stored with the data word in memory.Each check bit is a parity over a group of bits in the data word.When the word is read from memory, the associated parity bits are also read from memory and compared with a new set of check bits generated from the read data. If the check bits compare, it signifies that no error has occurred. If the check bits do not compare with the stored parity, they generate a unique pattern, called a syndrome, that can be used to identify the bit in error.A single error occurs when a bit changes in value from I to 0 or from 0 to 1 during the write or read operation If the specific bit in error is identified, then the error can be corrected by complementing the erroneous bit.Error-Detection and Correcting CodeError Correcting Code (Hamming Code) k parity bits are added to an n-bit data word, forming a new word of n + k bitsThe bit positions are numbered in sequence from 1 to n + kThose positions numbered as a power of 2 are reserved for the parity bitsThe remaining bits are the data bitsFor an 8-bit data word 11000100. We include four parity bits with the 8-bit word and arrange the 12 bits as follows:Four parity bits, P1, P2 P3, and P4 are in positions 1,2, 4, and 8, respectivelyError-Detection and Correcting Code(Hamming Code)The eight bits of the data word are in the remaining positions. Each parity bit is calculated as follows: Exclusive-OR operation performs the odd function. It is equal to 1 for an odd number of I's in the variables and to 0 for an even number of 1's. Thus, each parity bit is set so that the total number of 1's in the checked positions, including the parity bit, is always even.Error-Detection and Correcting Code (Hamming Code)The 8-bit data word is stored in memory together with the 4 parity bits as a 12-bit composite word. Substituting the four P bits in their proper positions, we obtain the 12-bit composite word stored in memory: When the 12 bits are read from memory, they are checked again for possible errors. The parity is checked over the same combination of bits including the parity bit. The four check bits are evaluated as follows: A 0 check bit designates an even parity over the checked bits and a 1 designates an odd parity. Since the bits were stored with even parity, the result, C = C1C2C4C8 = 0000, indicates that no error has occurred. However, if C ≠ 0, then the 4-bit binary number formed by the check bits gives the position of the erroneous bit. For example, consider the following three cases:Error-Detection and Correcting Code (Hamming Code) In the first case, there is no error in the 12-bit word. In the second case, there is an error in bit position number I because it changed from 0 to I. The third case shows an error in bit position 5 with a change from I to O. Evaluating the XOR of the corresponding bits, we determine the four check bits to be as follows:for no error, we have C = 0000; with an error in bit 1, we obtain C = 0001;and with an error in bit 5, we get C = 0101. The binary number of C, when it is notequal to 0000, gives the position of the bit in error. The error can be corrected by complementing the corresponding bit. Note that an error can occur in the data word or in one of the parity bits.SummaryMemories provide storage for computersMemories are organized in words Selected by addressesSRAMs store data in latchesAccessed by surrounding circuitryRAM waveforms indicate the control signals needed for accessWords in SRAMs are accessed with decodersOnly one word selected at a timeError correction and detection codes (Hamming)