Digital Logic Design - Lecture 28: Timing Analysis

Lecture 28Timing AnalysisOverviewCircuits do not respond instantaneously to input changesPredictable delay in transferring inputs to outputsPropagation delay Sequential circuits require a periodic clockGoal: analyze clock circuit to determine maximum clock frequencyRequires analysis of paths from flip-flop outputs to flip-flop inputsEven after inputs change, output signal of circuit maintains original output for short timeUnderstanding Sequential Circuit TimingTwo characteristics of a computer System Processor clock speed Size of its main memoryMain memory size (the number of storage bits in the computer)Clock speed involves analysis of the timing parameters of combinational and sequential circuit componentsSequential CircuitsSequential circuits can contain both combinational logic and edge-triggered flip flopsA clock signal determines when data is stored in flip flops Goal: How fast can the circuit operate?Minimum clock period: TminMaximum clock frequency: fmaxMaximum clock frequency is the inverse of the minimum clock period1/Tmin = fmax ClockPeriod ClockThe amount of time between rising clock edges is called the clock period, Tper, of the clockTiming Parameters for Combinational LogicPropagation delay (tpd) - This value indicates the amount of time needed for a change in a logic input to result in a permanent change at an output.Combinational logic is guaranteed not to show any further output changes in response to an input change after tpd time units have passed.Contamination delay (tcd) indicates the amount of time needed for a change in a logic input to result in an initial change at an output [1]. Combinational logic is guaranteed not to show any output change in response to an input change before tcd time units have passed.Timing Parameters for Combinational LogicAACombinational Logic Timing: InverterCombinational logic is made from electronic circuitsAn input change takes time to propagate to the outputThe output remains unchanged for a time period equal to the contamination delay, tcdThe new output value is guaranteed to valid after a time period equal to the propagation delay, tpdorAfter the propagation delay, tpd, the inverter output is stable and is guaranteed not to change again until another input change.AYtpdtcdAchange in Y is not instantaneous.Combinational Logic Timing: InverterCombinational propagation delays are additiveCombinational propagation delay, tpd is calculated by adding the propagation delays of the circuit components along the longest pathAYtpdtcdAchange in Y is not instantaneous.Combinational Logic Timing: XNOR GateThe output is guaranteed to be stable with old value until the contamination delayUnknown values shown in waveforms as XsThe output is guaranteed to be stable with the new value after the propagation delay Combinational Logic Timing: Complex CircuitsPropagation delays are additive Locate the longest combination of tpdContamination delays may not be additiveLocate the shortest path of tcdFind propagation and contamination delay of new, combined circuitABCABCCircuit XCircuit XTpd = 5nsTcd = 1nsTpd = 2nsTcd = 1nsTpd = 3nsTcd = 1nsTiming Parameters for Combinational LogicLongest delay from a circuit input (w, x, y) to the output z is the sum of the component propagation delays through gates A and B, 3 ns + 2 ns = 5 ns4 ns propagation delay path through gates C and B can be ignored in determining the overall propagation delay of the circuit since it is shorter than 5 nsTiming Parameters for Combinational LogicIn contrast, the determination of the contamination delay of the combined circuit requires identifying the shortest path of contamination delays from input to output.Contamination delay of the combined circuit is 2 ns, since the shortest sum of contamination delays from an input (y) to an output (z), is tcd(C) + tcd(B) = 1 ns + 1 ns = 2nsthis value is smaller than the contamination delay path through gates A and B (2 ns + 1ns = 3 ns)Timing Parameters for Sequential LogicSequential circuits, such as edge-triggered flip-flops exhibit certain timing characteristicsUnlike combinational, timing parameters for clocked devices are specified in relation to the clock input (rising edge)Flip-Flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered) or falling (for negative-edge triggered) clock edgePropagation delay (tClk−Q) - indicates the amount of time needed for a change in the flip flop-clock input (e.g. rising edge) resulting in a permanent change at the flip-flop output (Q).Contamination delay (tcd) - indicates the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q).Clocked Device: Contamination and Propagation DelayPropagation delay (tClk−Q) – indicates the amount of time needed for a change in the flip flop-clock input (e.g. rising edge) resulting in a permanent change at the flip-flop output (Q).Contamination delay (tcd) – indicates the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q).ClkQDtcdtClk-QClocked Device: Contamination and Propagation DelaySetup time (ts) - indicates the amount of time before the clock edge that data input D must be stable.Hold time (th) - indicates the amount of time after the clock edge that data input D must be held stable.Clocked Devices: Setup and Hold Times ts thClkQDTiming parameters for clocked devices are specified in relation to the clock input (rising edge)D input must be valid at least ts (setup time) before the rising clock edgeD input must be held steady th (hold time) after rising clock edgeSetup and hold are input restrictionsFailure to meet restrictions causes circuit to operate incorrectlyClocked Devices: Setup and Hold Times ts thClkQDTiming parameters for clocked devices are specified in relation to the clock input (rising edge)Setup (ts) and hold times (th) are restrictions that a flip-flop places on combinational or sequential circuitryThe circuit must be designed so that the D flip flop input signal arrives at least ‘ts‘ time units before the clock edge and does not change until at least ‘th‘ time units after the clock edge. that drives a flip-flop D input.If either of these restrictions are violated for any of the flip-flops in the circuit, the circuit will not operate correctlyThese restrictions limit the maximum clock frequency at which the circuit can operateEdge-Triggered Flip Flop TimingDCLKts = setup timeth = hold timeThe logic driving the flip flop must ensure that setup and hold are metTiming values (tcd tpd tClk-Q ts th) Analyzing Sequential CircuitsWhat is the minimum time between rising clock edges?Tmin = TCLK-Q (FFA) + Tpd (G) + Ts (FFB) Trace propagation delays from FFA to FFBDraw the waveforms!ZComb.Logic TClk-Q = 5 nsTs = 2 nsDQDQYXDCLKTClk-Q = 5nsTpd = 5nsFFAFFBGFmax = _______Analyzing Sequential CircuitsWhat is the minimum clock period (Tmin) of this circuit? Hint: evaluate all FF to FF pathsMaximum clock frequency is 1/TminZComb.Logic H TClk-Q = 4 nsTs = 2 nsDQDQYXCLKTClk-Q = 5nsTpd = 5nsFFAFFBComb.Logic F Tpd = 4nsAnalyzing Sequential CircuitsPath FFA to FFB TClk-Q(FFA) + Tpd(H) + Ts(FFB) = 5ns + 5ns + 2ns = 12nsPath FFB to FFBTCLK-Q(FFB) + Tpd(F) + Tpd(H) + Ts(FFB) = 4ns + 4ns + 5ns + 2ns ZComb.Logic H TClk-Q = 4 nsTs = 2 nsDQDQYXCLKTClk-Q = 5nsTpd = 5nsFFAFFBComb.Logic F Tpd = 4nsFmax = _______Analyzing Sequential Circuits: Hold Time ViolationOne more issue: make sure Y remains stable for hold time (Th) after rising clock edgeRemember: contamination delay ensures signal doesn’t changeHow long before first change arrives at Y?Tcd(FFA) + Tcd(G) >= Th1ns + 2ns > 2nsZComb.Logic Th = 2 nsDQDQYXDCLKTcd = 1nsTcd = 2nsFFAFFBGAnalyzing Sequential Circuits: Hold Time ViolationsPath FFA to FFB TCD(FFA) + TCD(H) > Th(FFB) = 1 ns + 2ns > 2nsPath FFB to FFBTCD(FFB) + TCD(F) + TCd(H) > Th(FFB) = 1ns + 1ns + 2ns > 2ns ZComb.Logic H TClD = 1 nsTh = 2 nsDQDQYXCLKTClD = 1nsTcd = 2nsFFAFFBComb.Logic F Tcd = 1nsAll paths must satisfy requirementsDetermining the Max. Clock Frequency for a Sequential CircuitMost digital circuits contain both combinational components (gates, muxes, adders, etc.) and sequential components (flip-flops).Combinational and sequential component parameters are considered in order to determine the maximum clock frequency at which a circuit will operate and generate correct results.Consider the flow of data in this circuit in response to a rising clock edge, starting at flip-flop A.Determining the Max. Clock Frequency for a Sequential CircuitFollowing the rising clock edge on Clk, a valid output appears on signal X after tClk−Q = 10 ns.A valid output Y appears at the output of inverter F, tpd = 5 ns after a valid X arrives at the gate.Signal Y is clocked into flip-flop B on the next rising clock edge. This signal must arrive at least ts = 2ns before the rising clock edge.Determining the Max. Clock Frequency for a Sequential CircuitMinimum clock period, Tmin of the circuitand the maximum clock frequency of the circuit is Determining the Max. Clock Frequency for a Sequential CircuitClk input is attached to both flip-flops, both will change value at the same time. On each clock edge, the same three steps starting from flip flop A are repeated.There are often millions of flip-flop to flip-flop paths that need to be considered in calculating the maximum clock frequency.Locate the longest path among all the flip-flop paths in the circuitValidating Flip-Flop Hold TimeDesigning a circuit for a specific maximum clock frequency is not enough to ensure that the circuit will work properlyHold time, th must be satisfied for each flip-flop input, indicating that each D input cannot change until th time units after the clock edgeContamination delays of combinational circuitry and flip-flops help prevent flip-flop inputs from changing instantaneouslyValidating Flip-Flop Hold TimeHold time requirement on flip-flop B indicates that the Y input to flip-flop B should not change until at least 2 ns after the rising clock edge of ClkThe earliest the signal can start to change is equal to the sum of the contamination delays of flip-flop A and inverter Xth, 2 ns, is less than tcd(A) + tcd(B), 4 ns,The hold time is satisfied and the circuit will work correctlyValidating Flip-Flop Hold TimeHold time requirement on flip-flop B indicates that the Y input to flip-flop B should not change until at least 2 ns after the rising clock edge of ClkHold time requirement on flip-flop B indicats that the Y input to flip-flop B should not change until at least 2 ns after the rising clock edge of ClkSequential Circuit TimingSequential circuits rely on a clock signal to control the movement of system dataGiven a set of combinational and sequential components and their associated timing parameters, it is possible to determine the maximum clock frequency that can be used with the circuitThis analysis includes the examination of every flip-flop to flip-flop path in the circuitMoreover it includes both the propagation delays along the paths and the data setup time at the destination flip-flop.Following the calculation of the maximum clock frequency, each flip-flop to flip-flop path can be examined to ensure that flip-flop hold times are satisfied.SummaryMaximum clock frequency is a fundamental parameter in sequential computer systemsPossible to determined clock frequency from propagation delays and setup timeThe longest path determines the clock frequenctAll flip-flop to flip-flop paths must be checkedHold time are satisfied by examining contamination delaysThe shortest contamination delay path determines if hold times are metCheck handout for more details and examples.