William stallings computer organization and architecture 6th edition - Chapter 5: Internal Memory

William Stallings Computer Organization and Architecture6th EditionChapter 5Internal MemorySemiconductor Memory TypesSemiconductor MemoryRAM Misnamed as all semiconductor memory is random accessRead/WriteVolatileTemporary storageStatic or dynamicMemory Cell OperationDynamic RAMBits stored as charge in capacitorsCharges leakNeed refreshing even when poweredSimpler constructionSmaller per bitLess expensiveNeed refresh circuitsSlowerMain memoryEssentially analogueLevel of charge determines valueDynamic RAM StructureDRAM OperationAddress line active when bit read or writtenTransistor switch closed (current flows)WriteVoltage to bit lineHigh for 1 low for 0Then signal address lineTransfers charge to capacitorReadAddress line selectedtransistor turns onCharge from capacitor fed via bit line to sense amplifierCompares with reference value to determine 0 or 1Capacitor charge must be restoredStatic RAMBits stored as on/off switchesNo charges to leakNo refreshing needed when poweredMore complex constructionLarger per bitMore expensiveDoes not need refresh circuitsFasterCacheDigitalUses flip-flopsStating RAM StructureStatic RAM OperationTransistor arrangement gives stable logic stateState 1C1 high, C2 lowT1 T4 off, T2 T3 onState 0C2 high, C1 lowT2 T3 off, T1 T4 onAddress line transistors T5 T6 is switchWrite – apply value to B & compliment to BRead – value is on line BSRAM v DRAMBoth volatilePower needed to preserve dataDynamic cell Simpler to build, smallerMore denseLess expensiveNeeds refreshLarger memory unitsStaticFasterCacheRead Only Memory (ROM)Permanent storageNonvolatileMicroprogramming (see later)Library subroutinesSystems programs (BIOS)Function tablesTypes of ROMWritten during manufactureVery expensive for small runsProgrammable (once)PROMNeeds special equipment to programRead “mostly”Erasable Programmable (EPROM)Erased by UVElectrically Erasable (EEPROM)Takes much longer to write than readFlash memoryErase whole memory electricallyOrganisation in detailA 16Mbit chip can be organised as 1M of 16 bit wordsA bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so onA 16Mbit chip can be organised as a 2048 x 2048 x 4bit arrayReduces number of address pinsMultiplex row address and column address11 pins to address (211=2048)Adding one more pin doubles range of values so x4 capacityRefreshingRefresh circuit included on chipDisable chipCount through rowsRead & Write backTakes timeSlows down apparent performanceTypical 16 Mb DRAM (4M x 4)PackagingModule OrganizationModule Organization (2)Error CorrectionHard FailurePermanent defectSoft ErrorRandom, non-destructiveNo permanent damage to memoryDetected using Hamming error correcting codeError Correcting Code FunctionAdvanced DRAM OrganizationBasic DRAM same since first RAM chipsEnhanced DRAMContains small SRAM as wellSRAM holds last line read (c.f. Cache!)Cache DRAMLarger SRAM componentUse as cache or serial bufferSynchronous DRAM (SDRAM)Access is synchronized with an external clockAddress is presented to RAMRAM finds data (CPU waits in conventional DRAM)Since SDRAM moves data in time with system clock, CPU knows when data will be readyCPU does not have to wait, it can do something elseBurst mode allows SDRAM to set up stream of data and fire it out in blockDDR-SDRAM sends data twice per clock cycle (leading & trailing edge)IBM 64Mb SDRAMSDRAM OperationRAMBUSAdopted by Intel for Pentium & ItaniumMain competitor to SDRAMVertical package – all pins on one sideData exchange over 28 wires < cm longBus addresses up to 320 RDRAM chips at 1.6GbpsAsynchronous block protocol480ns access timeThen 1.6 GbpsRAMBUS Diagram