Phần cứng - Chapter 12: CPU structure and function

William Stallings Computer Organization and Architecture6th EditionChapter 12CPU Structureand FunctionCPU StructureCPU must:Fetch instructionsInterpret instructionsFetch dataProcess dataWrite dataCPU With Systems BusCPU Internal StructureRegistersCPU must have some working space (temporary storage)Called registersNumber and function vary between processor designsOne of the major design decisionsTop level of memory hierarchyUser Visible RegistersGeneral PurposeDataAddressCondition CodesGeneral Purpose Registers (1)May be true general purposeMay be restrictedMay be used for data or addressingDataAccumulatorAddressingSegmentGeneral Purpose Registers (2)Make them general purposeIncrease flexibility and programmer optionsIncrease instruction size & complexityMake them specializedSmaller (faster) instructionsLess flexibilityHow Many GP Registers?Between 8 - 32Fewer = more memory referencesMore does not reduce memory references and takes up processor real estateSee also RISCHow big?Large enough to hold full addressLarge enough to hold full wordOften possible to combine two data registersC programmingdouble int a;long int a;Condition Code RegistersSets of individual bitse.g. result of last operation was zeroCan be read (implicitly) by programse.g. Jump if zeroCan not (usually) be set by programsControl & Status RegistersProgram CounterInstruction Decoding RegisterMemory Address RegisterMemory Buffer RegisterRevision: what do these all do?Program Status WordA set of bitsIncludes Condition CodesSign of last resultZeroCarryEqualOverflowInterrupt enable/disableSupervisorSupervisor ModeIntel ring zeroKernel modeAllows privileged instructions to executeUsed by operating systemNot available to user programsOther RegistersMay have registers pointing to:Process control blocks (see O/S)Interrupt Vectors (see O/S)N.B. CPU design and operating system design are closely linkedExample Register OrganizationsForeground ReadingStallings Chapter 12Manufacturer web sites & specsInstruction CycleRevisionStallings Chapter 3Indirect CycleMay require memory access to fetch operandsIndirect addressing requires more memory accessesCan be thought of as additional instruction subcycleInstruction Cycle with IndirectInstruction Cycle State DiagramData Flow (Instruction Fetch)Depends on CPU designIn general:FetchPC contains address of next instructionAddress moved to MARAddress placed on address busControl unit requests memory readResult placed on data bus, copied to MBR, then to IRMeanwhile PC incremented by 1Data Flow (Data Fetch)IR is examinedIf indirect addressing, indirect cycle is performedRight most N bits of MBR transferred to MARControl unit requests memory readResult (address of operand) moved to MBRData Flow (Fetch Diagram)Data Flow (Indirect Diagram)Data Flow (Execute)May take many formsDepends on instruction being executedMay includeMemory read/writeInput/OutputRegister transfersALU operationsData Flow (Interrupt)SimplePredictableCurrent PC saved to allow resumption after interruptContents of PC copied to MBRSpecial memory location (e.g. stack pointer) loaded to MARMBR written to memoryPC loaded with address of interrupt handling routineNext instruction (first of interrupt handler) can be fetchedData Flow (Interrupt Diagram)PrefetchFetch accessing main memoryExecution usually does not access main memoryCan fetch next instruction during execution of current instructionCalled instruction prefetchImproved PerformanceBut not doubled:Fetch usually shorter than executionPrefetch more than one instruction?Any jump or branch means that prefetched instructions are not the required instructionsAdd more stages to improve performancePipeliningFetch instructionDecode instructionCalculate operands (i.e. EAs)Fetch operandsExecute instructionsWrite resultOverlap these operationsTwo Stage Instruction PipelineTiming of PipelineBranch in a PipelineSix Stage Instruction PipelineAlternative Pipeline DepictionSpeedup Factors with Instruction PipeliningDealing with BranchesMultiple StreamsPrefetch Branch TargetLoop bufferBranch predictionDelayed branchingMultiple StreamsHave two pipelinesPrefetch each branch into a separate pipelineUse appropriate pipelineLeads to bus & register contentionMultiple branches lead to further pipelines being neededPrefetch Branch TargetTarget of branch is prefetched in addition to instructions following branchKeep target until branch is executedUsed by IBM 360/91Loop BufferVery fast memoryMaintained by fetch stage of pipelineCheck buffer before fetching from memoryVery good for small loops or jumpsc.f. cacheUsed by CRAY-1Loop Buffer DiagramBranch Prediction (1)Predict never takenAssume that jump will not happenAlways fetch next instruction 68020 & VAX 11/780VAX will not prefetch after branch if a page fault would result (O/S v CPU design)Predict always takenAssume that jump will happenAlways fetch target instructionBranch Prediction (2)Predict by OpcodeSome instructions are more likely to result in a jump than thersCan get up to 75% successTaken/Not taken switchBased on previous historyGood for loopsBranch Prediction (3)Delayed BranchDo not take jump until you have toRearrange instructionsBranch Prediction FlowchartBranch Prediction State DiagramDealing With BranchesIntel 80486 PipeliningFetchFrom cache or external memoryPut in one of two 16-byte prefetch buffersFill buffer with new data as soon as old data consumedAverage 5 instructions fetched per loadIndependent of other stages to keep buffers fullDecode stage 1Opcode & address-mode infoAt most first 3 bytes of instructionCan direct D2 stage to get rest of instructionDecode stage 2Expand opcode into control signalsComputation of complex address modesExecuteALU operations, cache access, register updateWritebackUpdate registers & flagsResults sent to cache & bus interface write buffers80486 Instruction Pipeline ExamplesPentium 4 RegistersEFLAGS RegisterControl RegistersMMX Register MappingMMX uses several 64 bit data typesUse 3 bit register address fields8 registersNo MMX specific registersAliasing to lower 64 bits of existing floating point registersPentium Interrupt ProcessingInterruptsMaskableNonmaskableExceptionsProcessor detectedProgrammedInterrupt vector tableEach interrupt type assigned a numberIndex to vector table256 * 32 bit interrupt vectors5 priority classesPowerPC User Visible RegistersPowerPC Register FormatsMMX Register Mapping DiagramForeground ReadingProcessor examplesStallings Chapter 12Web pages etc.