William stallings computer organization and architecture 6th edition - Chapter 3: System buses

William Stallings Computer Organization and Architecture6th EditionChapter 3System BusesProgram ConceptHardwired systems are inflexibleGeneral purpose hardware can do different tasks, given correct control signalsInstead of re-wiring, supply a new set of control signalsWhat is a program?A sequence of stepsFor each step, an arithmetic or logical operation is doneFor each operation, a different set of control signals is neededFunction of Control UnitFor each operation a unique code is providede.g. ADD, MOVEA hardware segment accepts the code and issues the control signalsWe have a computer!ComponentsThe Control Unit and the Arithmetic and Logic Unit constitute the Central Processing UnitData and instructions need to get into the system and results outInput/outputTemporary storage of code and results is neededMain memoryComputer Components:Top Level ViewInstruction CycleTwo steps:FetchExecuteFetch CycleProgram Counter (PC) holds address of next instruction to fetchProcessor fetches instruction from memory location pointed to by PCIncrement PCUnless told otherwiseInstruction loaded into Instruction Register (IR)Processor interprets instruction and performs required actionsExecute CycleProcessor-memorydata transfer between CPU and main memoryProcessor I/OData transfer between CPU and I/O moduleData processingSome arithmetic or logical operation on dataControlAlteration of sequence of operationse.g. jumpCombination of aboveExample of Program ExecutionInstruction Cycle - State DiagramInterruptsMechanism by which other modules (e.g. I/O) may interrupt normal sequence of processingPrograme.g. overflow, division by zeroTimerGenerated by internal processor timerUsed in pre-emptive multi-taskingI/Ofrom I/O controllerHardware failuree.g. memory parity errorProgram Flow ControlInterrupt CycleAdded to instruction cycleProcessor checks for interruptIndicated by an interrupt signalIf no interrupt, fetch next instructionIf interrupt pending:Suspend execution of current program Save contextSet PC to start address of interrupt handler routineProcess interruptRestore context and continue interrupted programTransfer of Control via InterruptsInstruction Cycle with InterruptsProgram TimingShort I/O WaitProgram TimingLong I/O WaitInstruction Cycle (with Interrupts) - State DiagramMultiple InterruptsDisable interruptsProcessor will ignore further interrupts whilst processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occurDefine prioritiesLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed, processor returns to previous interruptMultiple Interrupts - SequentialMultiple Interrupts – NestedTime Sequence of Multiple InterruptsConnectingAll the units must be connectedDifferent type of connection for different type of unitMemoryInput/OutputCPUComputer ModulesMemory ConnectionReceives and sends dataReceives addresses (of locations)Receives control signals ReadWriteTimingInput/Output Connection(1)Similar to memory from computer’s viewpointOutputReceive data from computerSend data to peripheralInputReceive data from peripheralSend data to computerInput/Output Connection(2)Receive control signals from computerSend control signals to peripheralse.g. spin diskReceive addresses from computere.g. port number to identify peripheralSend interrupt signals (control)CPU ConnectionReads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interruptsBusesThere are a number of possible interconnection systemsSingle and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)What is a Bus?A communication pathway connecting two or more devicesUsually broadcast Often groupedA number of channels in one buse.g. 32 bit data bus is 32 separate single bit channelsPower lines may not be shownData BusCarries dataRemember that there is no difference between “data” and “instruction” at this levelWidth is a key determinant of performance8, 16, 32, 64 bitAddress busIdentify the source or destination of datae.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of systeme.g. 8080 has 16 bit address bus giving 64k address spaceControl BusControl and timing informationMemory read/write signalInterrupt requestClock signalsBus Interconnection SchemeBig and Yellow?What do buses look like?Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boardse.g. PCISets of wiresSingle Bus ProblemsLots of devices on one bus leads to:Propagation delaysLong data paths mean that co-ordination of bus use can adversely affect performanceIf aggregate data transfer approaches bus capacityMost systems use multiple buses to overcome these problemsTraditional (ISA)(with cache)High Performance BusBus TypesDedicatedSeparate data & address linesMultiplexedShared linesAddress valid or data valid control lineAdvantage - fewer linesDisadvantagesMore complex controlUltimate performanceBus ArbitrationMore than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributedCentralised ArbitrationSingle hardware device controlling bus accessBus ControllerArbiterMay be part of CPU or separateDistributed ArbitrationEach module may claim the busControl logic on all modulesTimingCo-ordination of events on busSynchronousEvents determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an eventSynchronous Timing DiagramAsynchronous Timing – Read DiagramAsynchronous Timing – Write DiagramPCI BusPeripheral Component InterconnectionIntel released to public domain32 or 64 bit50 linesPCI Bus Lines (required)Systems linesIncluding clock and resetAddress & Data32 time mux lines for address/dataInterrupt & validate linesInterface ControlArbitrationNot sharedDirect connection to PCI bus arbiterError linesPCI Bus Lines (Optional)Interrupt linesNot sharedCache support64-bit Bus ExtensionAdditional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit transferJTAG/Boundary ScanFor testing proceduresPCI CommandsTransaction between initiator (master) and targetMaster claims busDetermine type of transactione.g. I/O read/writeAddress phaseOne or more data phasesPCI Read Timing DiagramPCI Bus ArbitrationForeground ReadingStallings, chapter 3 (all of it)www.pcguide.com/ref/mbsys/buses/In fact, read the whole site!www.pcguide.com/